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anv: emit 3DSTATE_HS in cmd_buffer_flush_gfx_state

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Patch packs 3DSTATE_HS state during pipeline creation but it
gets emitted only before 3DPRIMITIVE. We will later need this
to implement a workaround.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21308>
This commit is contained in:
Tapani Pälli 2023-02-09 16:34:54 +02:00 • committed by Marge Bot
parent a043ae8e24
commit 2028f1caa3
3 changed files with 47 additions and 35 deletions
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1
src/intel/vulkan/anv_private.h
View file

@ -3145,6 +3145,7 @@ struct anv_graphics_pipeline {
uint32_t wm[2]; uint32_t wm[2];
uint32_t blend_state[1 + MAX_RTS * 2]; uint32_t blend_state[1 + MAX_RTS * 2];
uint32_t streamout_state[5]; uint32_t streamout_state[5];
uint32_t hs[9];
} gfx8; } gfx8;
}; };

7
src/intel/vulkan/genX_cmd_buffer.c
View file

@ -3522,6 +3522,13 @@ genX(cmd_buffer_flush_gfx_state)(struct anv_cmd_buffer *cmd_buffer)
} }
} }
if (cmd_buffer->state.gfx.dirty & ANV_CMD_DIRTY_PIPELINE) {
uint32_t *dw =
anv_batch_emitn(&cmd_buffer->batch, GENX(3DSTATE_HS_length),
GENX(3DSTATE_HS));
memcpy(dw, &pipeline->gfx8.hs, sizeof(pipeline->gfx8.hs));
}
if (any_dynamic_state_dirty || cmd_buffer->state.gfx.dirty) if (any_dynamic_state_dirty || cmd_buffer->state.gfx.dirty)
genX(cmd_buffer_flush_dynamic_state)(cmd_buffer); genX(cmd_buffer_flush_dynamic_state)(cmd_buffer);
} }

74
src/intel/vulkan/genX_pipeline.c
View file

@ -1311,56 +1311,60 @@ emit_3dstate_hs_ds(struct anv_graphics_pipeline *pipeline,
const struct brw_tcs_prog_data *tcs_prog_data = get_tcs_prog_data(pipeline); const struct brw_tcs_prog_data *tcs_prog_data = get_tcs_prog_data(pipeline);
const struct brw_tes_prog_data *tes_prog_data = get_tes_prog_data(pipeline); const struct brw_tes_prog_data *tes_prog_data = get_tes_prog_data(pipeline);
anv_batch_emit(&pipeline->base.batch, GENX(3DSTATE_HS), hs) { struct GENX(3DSTATE_HS) hs = {
hs.Enable = true; GENX(3DSTATE_HS_header),
hs.StatisticsEnable = true; };
hs.KernelStartPointer = tcs_bin->kernel.offset;
/* Wa_1606682166 */ hs.Enable = true;
hs.SamplerCount = GFX_VER == 11 ? 0 : get_sampler_count(tcs_bin); hs.StatisticsEnable = true;
hs.BindingTableEntryCount = tcs_bin->bind_map.surface_count; hs.KernelStartPointer = tcs_bin->kernel.offset;
/* Wa_1606682166 */
hs.SamplerCount = GFX_VER == 11 ? 0 : get_sampler_count(tcs_bin);
hs.BindingTableEntryCount = tcs_bin->bind_map.surface_count;
#if GFX_VER >= 12 #if GFX_VER >= 12
/* Wa_1604578095: /* Wa_1604578095:
* *
* Hang occurs when the number of max threads is less than 2 times * Hang occurs when the number of max threads is less than 2 times
* the number of instance count. The number of max threads must be * the number of instance count. The number of max threads must be
* more than 2 times the number of instance count. * more than 2 times the number of instance count.
*/ */
assert((devinfo->max_tcs_threads / 2) > tcs_prog_data->instances); assert((devinfo->max_tcs_threads / 2) > tcs_prog_data->instances);
#endif #endif
hs.MaximumNumberofThreads = devinfo->max_tcs_threads - 1; hs.MaximumNumberofThreads = devinfo->max_tcs_threads - 1;
hs.IncludeVertexHandles = true; hs.IncludeVertexHandles = true;
hs.InstanceCount = tcs_prog_data->instances - 1; hs.InstanceCount = tcs_prog_data->instances - 1;
hs.VertexURBEntryReadLength = 0; hs.VertexURBEntryReadLength = 0;
hs.VertexURBEntryReadOffset = 0; hs.VertexURBEntryReadOffset = 0;
hs.DispatchGRFStartRegisterForURBData = hs.DispatchGRFStartRegisterForURBData =
tcs_prog_data->base.base.dispatch_grf_start_reg & 0x1f; tcs_prog_data->base.base.dispatch_grf_start_reg & 0x1f;
#if GFX_VER >= 12 #if GFX_VER >= 12
hs.DispatchGRFStartRegisterForURBData5 = hs.DispatchGRFStartRegisterForURBData5 =
tcs_prog_data->base.base.dispatch_grf_start_reg >> 5; tcs_prog_data->base.base.dispatch_grf_start_reg >> 5;
#endif #endif
#if GFX_VERx10 >= 125 #if GFX_VERx10 >= 125
hs.ScratchSpaceBuffer = hs.ScratchSpaceBuffer =
get_scratch_surf(&pipeline->base, MESA_SHADER_TESS_CTRL, tcs_bin); get_scratch_surf(&pipeline->base, MESA_SHADER_TESS_CTRL, tcs_bin);
#else #else
hs.PerThreadScratchSpace = get_scratch_space(tcs_bin); hs.PerThreadScratchSpace = get_scratch_space(tcs_bin);
hs.ScratchSpaceBasePointer = hs.ScratchSpaceBasePointer =
get_scratch_address(&pipeline->base, MESA_SHADER_TESS_CTRL, tcs_bin); get_scratch_address(&pipeline->base, MESA_SHADER_TESS_CTRL, tcs_bin);
#endif #endif
#if GFX_VER == 12 #if GFX_VER == 12
/* Patch Count threshold specifies the maximum number of patches that /* Patch Count threshold specifies the maximum number of patches that
* will be accumulated before a thread dispatch is forced. * will be accumulated before a thread dispatch is forced.
*/ */
hs.PatchCountThreshold = tcs_prog_data->patch_count_threshold; hs.PatchCountThreshold = tcs_prog_data->patch_count_threshold;
#endif #endif
hs.DispatchMode = tcs_prog_data->base.dispatch_mode; hs.DispatchMode = tcs_prog_data->base.dispatch_mode;
hs.IncludePrimitiveID = tcs_prog_data->include_primitive_id; hs.IncludePrimitiveID = tcs_prog_data->include_primitive_id;
}
GENX(3DSTATE_HS_pack)(NULL, pipeline->gfx8.hs, &hs);
anv_batch_emit(&pipeline->base.batch, GENX(3DSTATE_DS), ds) { anv_batch_emit(&pipeline->base.batch, GENX(3DSTATE_DS), ds) {
ds.Enable = true; ds.Enable = true;