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freedreno/registers: Add gen8 perfcntr support

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A few gen8 perfcntr groups have additional slice related SEL regs to
program.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40522>
This commit is contained in:
Rob Clark 2026-04-16 07:52:57 -07:00 • committed by Marge Bot
parent 2093153ba4
commit 1fd18a9734
2 changed files with 14 additions and 3 deletions
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4
src/freedreno/perfcntrs/freedreno_perfcntr.h
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@ -26,8 +26,10 @@ extern "C" {
/* Describes a single counter: */
struct fd_perfcntr_counter {
/* offset of the select register to choose what to count: */
/* offset of the SELect register to choose what to count: */
unsigned select_reg;
/* additional SEL regs to enable slice counters (gen8+) */
unsigned slice_select_regs[2];
/* offset of the lo/hi 32b to read current counter value: */
unsigned counter_reg_lo;
unsigned counter_reg_hi;

13
src/freedreno/registers/gen_header.py
View file

@ -1135,12 +1135,21 @@ def dump_perfcntrs(args):
(counter_lo, counter_hi) = get_counter()
select = get_reg(group['select'])
select_offset = 0
if "select_offset" in group:
select = select + int(group["select_offset"])
select_offset = int(group["select_offset"])
select = select + select_offset
slice_select_str = ""
if "slice_select" in group:
slice_select = group["slice_select"]
for reg in slice_select:
val = get_reg(reg) + select_offset
slice_select_str += "0x%04x, " % val
# TODO add support for things that need enable/clear regs
print(" { 0x%04x, 0x%04x, 0x%04x }," % (select, counter_lo, counter_hi))
print(" { 0x%04x, {%s}, 0x%04x, 0x%04x }," % (select, slice_select_str, counter_lo, counter_hi))
print("};")
print()