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radeonsi/video: Remove old VCN and UVD decode implementation

Browse source 
Only ac_video_dec is now used.

Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39627>
This commit is contained in:
David Rosca 2026-01-22 17:25:52 +01:00 • committed by Marge Bot
parent 26979becec
commit 1fad2ae6e1
10 changed files with 0 additions and 5288 deletions
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86
src/gallium/drivers/radeonsi/cencdecryptionparam.h
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@ -1,86 +0,0 @@
/**************************************************************************
*
* Copyright 2025 Advanced Micro Devices, Inc.
*
* SPDX-License-Identifier: MIT
*
**************************************************************************/
#ifndef SECURE_BUFFER_FORMAT_H
#define SECURE_BUFFER_FORMAT_H
#include <stdint.h>
#define AES_BLOCK_SIZE 16
#define KEY_SIZE_128 16
#define CMAC_SIZE AES_BLOCK_SIZE
#define MAX_SUBSAMPLES 288 /* Maximum subsamples in a sample */
typedef struct PACKED _secure_buffer_header
{
uint8_t cookie[8]; /* 8-byte cookie with value 'wvcencsb' */
uint8_t version; /* Set to 1 */
uint8_t reserved[55]; /* Reserved for future use */
} secure_buffer_header;
typedef struct PACKED _subsample_description
{
uint32_t num_bytes_clear;
uint32_t num_bytes_encrypted;
uint8_t subsample_flags; /* Is this the first/last subsample in a sample? */
uint8_t block_offset; /* Used only for CTR "cenc" mode */
} subsample_description;
typedef struct PACKED _cenc_encrypt_pattern_desc
{
uint32_t encrypt; /* Number of 16 byte blocks to decrypt */
uint32_t skip; /* Number of 16 byte blocks to leave in clear */
} cenc_encrypt_pattern_desc;
typedef struct PACKED _sample_description
{
subsample_description subsamples[MAX_SUBSAMPLES];
uint8_t iv[AES_BLOCK_SIZE]; /* The IV for the initial subsample */
cenc_encrypt_pattern_desc pattern;
uint32_t subsamples_length; /* The number of subsamples in the sample */
} sample_description;
typedef struct PACKED _native_enforce_policy_info
{
uint8_t enabled_policy_index[4];
uint32_t policy_array[32];
} native_enforce_policy_info;
typedef struct PACKED _signed_native_enforce_policy
{
uint8_t wrapped_key[KEY_SIZE_128];
native_enforce_policy_info native_policy;
uint8_t signature[CMAC_SIZE];
} signed_native_enforce_policy;
typedef struct PACKED hw_drm_key_blob_info
{
uint8_t wrapped_key[KEY_SIZE_128]; /* Content key encrypted with session key */
uint8_t wrapped_key_iv[AES_BLOCK_SIZE]; /* IV used to encrypt content key */
union
{
struct
{
uint32_t drm_session_id : 4; /* DRM Session ID */
uint32_t use_hw_drm_aes_ctr : 1; /* Invoke HW-DRM with AES-CTR for content decryption */
uint32_t use_hw_drm_aes_cbc : 1; /* Invoke HW-DRM with AES-CBC for content decryption */
uint32_t reserved_bits : 26; /* Reserved fields */
} s;
uint32_t value;
} u;
signed_native_enforce_policy local_policy;
uint8_t reserved[128];
} hw_drm_key_blob_info;
typedef struct PACKED amd_secure_buffer_format
{
secure_buffer_header sb_header;
sample_description desc;
hw_drm_key_blob_info key_blob;
} amd_secure_buffer_format;
#endif /* SECURE_BUFFER_FORMAT_H */

7
src/gallium/drivers/radeonsi/meson.build
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@ -88,19 +88,12 @@ files_libradeonsi = files(
'si_vpe.h',
'si_video_dec.h',
'si_video_dec.c',
'pspdecryptionparam.h',
'cencdecryptionparam.h',
'radeon_uvd.c',
'radeon_uvd.h',
'radeon_uvd_enc.c',
'radeon_uvd_enc.h',
'radeon_vce.c',
'radeon_vce.h',
'radeon_vcn.h',
'radeon_vcn.c',
'radeon_vcn_dec.c',
'radeon_vcn_dec.h',
'radeon_vcn_dec_jpeg.c',
'radeon_vcn_enc.c',
'radeon_vcn_enc.h',
'radeon_vcn_enc_1_2.c',

31
src/gallium/drivers/radeonsi/pspdecryptionparam.h
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@ -1,31 +0,0 @@
/**************************************************************************
*
* Copyright 2020 Advanced Micro Devices, Inc.
*
* SPDX-License-Identifier: MIT
*
**************************************************************************/
#ifndef _PSP_DECRYPTION_PARAM_H_
#define _PSP_DECRYPTION_PARAM_H_
typedef struct _DECRYPT_PARAMETERS_
{
uint32_t frame_size; // Size of encrypted frame
uint8_t encrypted_iv[16]; // IV of the encrypted frame (clear)
uint8_t encrypted_key[16]; // key to decrypt encrypted frame (encrypted with session key)
uint8_t session_iv[16]; // IV to be used to decrypt encrypted_key
union
{
struct
{
uint32_t drm_id : 4; //DRM session ID
uint32_t ctr : 1;
uint32_t cbc : 1;
uint32_t reserved : 26;
} s;
uint32_t value;
} u;
} DECRYPT_PARAMETERS;
#endif //_PSP_DECRYPTION_PARAM_H_

1389
src/gallium/drivers/radeonsi/radeon_uvd.c
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File diff suppressed because it is too large Load diff

28
src/gallium/drivers/radeonsi/radeon_uvd.h
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@ -1,28 +0,0 @@
/**************************************************************************
*
* Copyright 2011 Advanced Micro Devices, Inc.
*
* SPDX-License-Identifier: MIT
*
**************************************************************************/
#ifndef RADEON_UVD_H
#define RADEON_UVD_H
#include "winsys/radeon_winsys.h"
#include "vl/vl_video_buffer.h"
#include "ac_uvd_dec.h"
/* driver dependent callback */
typedef struct pb_buffer_lean *(*ruvd_set_dtb)(struct ruvd_msg *msg, struct vl_video_buffer *vb);
/* create an UVD decode */
struct pipe_video_codec *si_common_uvd_create_decoder(struct pipe_context *context,
const struct pipe_video_codec *templat,
ruvd_set_dtb set_dtb);
/* fill decoding target field from the luma and chroma surfaces */
void si_uvd_set_dt_surfaces(struct ruvd_msg *msg, const struct radeon_surf *luma,
const struct radeon_surf *chroma, enum ruvd_surface_type type);
#endif

3130
src/gallium/drivers/radeonsi/radeon_vcn_dec.c
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File diff suppressed because it is too large Load diff

164
src/gallium/drivers/radeonsi/radeon_vcn_dec.h
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@ -1,164 +0,0 @@
/**************************************************************************
*
* Copyright 2017 Advanced Micro Devices, Inc.
*
* SPDX-License-Identifier: MIT
*
**************************************************************************/
#ifndef _RADEON_VCN_DEC_H
#define _RADEON_VCN_DEC_H
#include "radeon_vcn.h"
#include "util/list.h"
#include "ac_vcn_dec.h"
#define NUM_BUFFERS 4
#define MAX_JPEG_INST 64
#define RADEON_DEC_ERR(fmt, args...) \
do { \
dec->error = true; \
mesa_loge("%s:%d %s VCN - " fmt, __FILE__, __LINE__, __func__, ##args); \
} while(0)
struct rvcn_dec_dynamic_dpb_t2 {
struct list_head list;
uint8_t index;
struct pipe_resource *buf;
};
struct jpeg_registers {
#define RDECODE_JPEG_REG_VER_V1 0
#define RDECODE_JPEG_REG_VER_V2 1
#define RDECODE_JPEG_REG_VER_V3 2
unsigned version;
unsigned jpeg_dec_soft_rst;
unsigned jrbc_ib_cond_rd_timer;
unsigned jrbc_ib_ref_data;
unsigned lmi_jpeg_read_64bit_bar_high;
unsigned lmi_jpeg_read_64bit_bar_low;
unsigned jpeg_rb_base;
unsigned jpeg_rb_size;
unsigned jpeg_rb_wptr;
unsigned jpeg_pitch;
unsigned jpeg_uv_pitch;
unsigned dec_addr_mode;
unsigned dec_y_gfx10_tiling_surface;
unsigned dec_uv_gfx10_tiling_surface;
unsigned lmi_jpeg_write_64bit_bar_high;
unsigned lmi_jpeg_write_64bit_bar_low;
unsigned jpeg_tier_cntl2;
unsigned jpeg_outbuf_rptr;
unsigned jpeg_outbuf_cntl;
unsigned jpeg_int_en;
unsigned jpeg_cntl;
unsigned jpeg_rb_rptr;
unsigned jpeg_outbuf_wptr;
unsigned jpeg_luma_base0_0;
unsigned jpeg_chroma_base0_0;
unsigned jpeg_chromav_base0_0;
unsigned jpeg_index;
unsigned jpeg_data;
};
struct radeon_decoder {
struct pipe_video_codec base;
unsigned stream_handle;
unsigned stream_type;
unsigned frame_number;
unsigned db_alignment;
unsigned dpb_size;
unsigned max_width;
unsigned max_height;
unsigned addr_gfx_mode;
struct pipe_screen *screen;
struct radeon_winsys *ws;
struct radeon_cmdbuf cs;
void *msg;
uint32_t *fb;
uint8_t *it;
uint8_t *probs;
void *bs_ptr;
rvcn_decode_buffer_t *decode_buffer;
bool vcn_dec_sw_ring;
struct rvcn_sq_var sq;
struct si_resource **msg_fb_it_probs_buffers;
unsigned num_dec_bufs;
struct si_resource **bs_buffers;
struct si_resource *dpb;
struct si_resource *ctx;
struct si_resource *sessionctx;
struct si_resource *subsample;
unsigned bs_size;
unsigned cur_buffer;
void *render_pic_list[32];
unsigned h264_valid_ref_num[17];
unsigned h264_valid_poc_num[34];
unsigned av1_version;
unsigned ref_idx;
bool tmz_ctx;
struct {
unsigned data0;
unsigned data1;
unsigned cmd;
unsigned cntl;
} reg;
struct jpeg_params jpg;
struct jpeg_registers jpg_reg;
enum {
DPB_MAX_RES = 0,
DPB_DYNAMIC_TIER_1,
DPB_DYNAMIC_TIER_2,
DPB_DYNAMIC_TIER_3,
} dpb_type;
struct {
enum {
CODEC_8_BITS = 0,
CODEC_10_BITS,
CODEC_12_BITS
} bts;
uint8_t index;
unsigned ref_size;
unsigned num_refs;
uint8_t ref_list[16];
struct {
uint8_t index;
struct pipe_video_buffer *buf;
} bufs[16];
} ref_codec;
struct list_head dpb_ref_list;
struct list_head dpb_unref_list;
bool (*send_cmd)(struct radeon_decoder *dec, struct pipe_video_buffer *target,
struct pipe_picture_desc *picture);
/* Additional contexts for mJPEG */
struct radeon_cmdbuf *jcs;
struct radeon_winsys_ctx **jctx;
unsigned cb_idx;
unsigned njctx;
bool error;
struct pipe_context *ectx;
struct pipe_video_codec *vpe;
};
bool send_cmd_dec(struct radeon_decoder *dec, struct pipe_video_buffer *target,
struct pipe_picture_desc *picture);
bool send_cmd_jpeg(struct radeon_decoder *dec, struct pipe_video_buffer *target,
struct pipe_picture_desc *picture);
struct pipe_video_codec *radeon_create_decoder(struct pipe_context *context,
const struct pipe_video_codec *templat);
#endif

436
src/gallium/drivers/radeonsi/radeon_vcn_dec_jpeg.c
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@ -1,436 +0,0 @@
/**************************************************************************
*
* Copyright 2018 Advanced Micro Devices, Inc.
*
* SPDX-License-Identifier: MIT
*
**************************************************************************/
#include "pipe/p_video_codec.h"
#include "radeon_vcn_dec.h"
#include "radeon_video.h"
#include "radeonsi/si_pipe.h"
#include "util/u_memory.h"
#include "util/u_video.h"
#include "ac_vcn_dec.h"
#include "amd/addrlib/inc/addrtypes.h"
#include <assert.h>
#include <stdio.h>
static struct pb_buffer_lean *radeon_jpeg_get_decode_param(struct radeon_decoder *dec,
struct pipe_video_buffer *target,
struct pipe_picture_desc *picture)
{
struct si_context *sctx = (struct si_context *)dec->base.context;
struct si_texture *luma = (struct si_texture *)((struct vl_video_buffer *)target)->resources[0];
struct si_texture *chroma, *chromav;
dec->jpg.bsd_size = align(dec->bs_size, 128);
dec->jpg.dt_luma_top_offset = luma->surface.u.gfx9.surf_offset | (luma->surface.tile_swizzle << 8);
dec->jpg.dt_chroma_top_offset = 0;
dec->jpg.dt_chromav_top_offset = 0;
dec->jpg.dt_swizzle_mode = luma->surface.u.gfx9.swizzle_mode;
if (sctx->gfx_level >= GFX12) {
switch (dec->jpg.dt_swizzle_mode) {
case ADDR3_256B_2D:
case ADDR3_4KB_2D:
case ADDR3_64KB_2D:
case ADDR3_256KB_2D:
dec->jpg.dt_addr_mode = RDECODE_TILE_8X8;
break;
case ADDR3_LINEAR:
default:
dec->jpg.dt_addr_mode = RDECODE_TILE_LINEAR;
break;
}
} else {
switch (dec->jpg.dt_swizzle_mode) {
case ADDR_SW_256B_D:
case ADDR_SW_4KB_D:
case ADDR_SW_64KB_D:
case ADDR_SW_4KB_D_X:
case ADDR_SW_64KB_D_X:
case ADDR_SW_256KB_S_X:
case ADDR_SW_256KB_D_X:
case ADDR_SW_256KB_R_X:
dec->jpg.dt_addr_mode = RDECODE_TILE_8X8;
break;
case ADDR_SW_256B_S:
case ADDR_SW_4KB_S:
case ADDR_SW_64KB_S:
case ADDR_SW_4KB_S_X:
case ADDR_SW_64KB_S_X:
case ADDR_SW_64KB_R_X:
dec->jpg.dt_addr_mode = RDECODE_TILE_32AS8;
break;
case ADDR_SW_LINEAR:
default:
dec->jpg.dt_addr_mode = RDECODE_TILE_LINEAR;
break;
}
}
switch (target->buffer_format) {
case PIPE_FORMAT_Y8_U8_V8_444_UNORM:
case PIPE_FORMAT_Y8_U8_V8_440_UNORM:
case PIPE_FORMAT_R8_G8_B8_UNORM:
chromav = (struct si_texture *)((struct vl_video_buffer *)target)->resources[2];
dec->jpg.dt_chromav_top_offset = chromav->surface.u.gfx9.surf_offset;
chroma = (struct si_texture *)((struct vl_video_buffer*)target)->resources[1];
dec->jpg.dt_chroma_top_offset =
chroma->surface.u.gfx9.surf_offset | (chroma->surface.tile_swizzle << 8);
dec->jpg.dt_uv_pitch = chroma->surface.u.gfx9.surf_pitch * chroma->surface.bpe;
break;
case PIPE_FORMAT_NV12:
chroma = (struct si_texture *)((struct vl_video_buffer*)target)->resources[1];
dec->jpg.dt_chroma_top_offset =
chroma->surface.u.gfx9.surf_offset | (chroma->surface.tile_swizzle << 8);
dec->jpg.dt_uv_pitch = chroma->surface.u.gfx9.surf_pitch * chroma->surface.bpe;
break;
case PIPE_FORMAT_YUYV:
case PIPE_FORMAT_Y8_400_UNORM:
case PIPE_FORMAT_R8G8B8A8_UNORM:
case PIPE_FORMAT_A8R8G8B8_UNORM:
break;
default:
assert(0);
break;
}
dec->jpg.dt_pitch = luma->surface.u.gfx9.surf_pitch * luma->surface.blk_w;
return luma->buffer.buf;
}
/* add a new set register command to the IB */
static void set_reg_jpeg(struct radeon_decoder *dec, unsigned reg, unsigned cond, unsigned type,
uint32_t val)
{
radeon_emit(&dec->jcs[dec->cb_idx], RDECODE_PKTJ(reg, cond, type));
radeon_emit(&dec->jcs[dec->cb_idx], val);
}
/* send a bitstream buffer command */
static void send_cmd_bitstream(struct radeon_decoder *dec, struct pb_buffer_lean *buf, uint32_t off,
unsigned usage, enum radeon_bo_domain domain)
{
uint64_t addr;
// jpeg soft reset
set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_JPEG_CNTL), COND0, TYPE0, 1);
// ensuring the Reset is asserted in SCLK domain
set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_CTX_INDEX), COND0, TYPE0, 0x01C2);
set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE0, 0x01400200);
set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_CTX_INDEX), COND0, TYPE0, 0x01C3);
set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE0, (1 << 9));
set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_SOFT_RESET), COND0, TYPE3, (1 << 9));
// wait mem
set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_JPEG_CNTL), COND0, TYPE0, 0);
// ensuring the Reset is de-asserted in SCLK domain
set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_CTX_INDEX), COND0, TYPE0, 0x01C3);
set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE0, (0 << 9));
set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_SOFT_RESET), COND0, TYPE3, (1 << 9));
dec->ws->cs_add_buffer(&dec->jcs[dec->cb_idx], buf, usage | RADEON_USAGE_SYNCHRONIZED, domain);
addr = dec->ws->buffer_get_virtual_address(buf);
addr = addr + off;
// set UVD_LMI_JPEG_READ_64BIT_BAR_LOW/HIGH based on bitstream buffer address
set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_LMI_JPEG_READ_64BIT_BAR_HIGH), COND0, TYPE0,
(addr >> 32));
set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_LMI_JPEG_READ_64BIT_BAR_LOW), COND0, TYPE0, addr);
// set jpeg_rb_base
set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_JPEG_RB_BASE), COND0, TYPE0, 0);
// set jpeg_rb_base
set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_JPEG_RB_SIZE), COND0, TYPE0, 0xFFFFFFF0);
// set jpeg_rb_wptr
set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_JPEG_RB_WPTR), COND0, TYPE0, (dec->jpg.bsd_size >> 2));
}
/* send a target buffer command */
static void send_cmd_target(struct radeon_decoder *dec, struct pb_buffer_lean *buf, uint32_t off,
unsigned usage, enum radeon_bo_domain domain)
{
uint64_t addr;
set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_JPEG_PITCH), COND0, TYPE0, (dec->jpg.dt_pitch >> 4));
set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_JPEG_UV_PITCH), COND0, TYPE0, (dec->jpg.dt_uv_pitch >> 4));
set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_JPEG_TILING_CTRL), COND0, TYPE0,
dec->jpg.dt_addr_mode | (dec->jpg.dt_swizzle_mode << 3));
set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_JPEG_UV_TILING_CTRL), COND0, TYPE0,
dec->jpg.dt_addr_mode | (dec->jpg.dt_swizzle_mode << 3));
dec->ws->cs_add_buffer(&dec->jcs[dec->cb_idx], buf, usage | RADEON_USAGE_SYNCHRONIZED, domain);
addr = dec->ws->buffer_get_virtual_address(buf);
addr = addr + off;
// set UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW/HIGH based on target buffer address
set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH), COND0, TYPE0,
(addr >> 32));
set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW), COND0, TYPE0, addr);
// set output buffer data address
set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_JPEG_INDEX), COND0, TYPE0, 0);
set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_JPEG_DATA), COND0, TYPE0, dec->jpg.dt_luma_top_offset);
set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_JPEG_INDEX), COND0, TYPE0, 1);
set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_JPEG_DATA), COND0, TYPE0, dec->jpg.dt_chroma_top_offset);
set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_JPEG_TIER_CNTL2), COND0, TYPE3, 0);
// set output buffer read pointer
set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_JPEG_OUTBUF_RPTR), COND0, TYPE0, 0);
// enable error interrupts
set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_JPEG_INT_EN), COND0, TYPE0, 0xFFFFFFFE);
// start engine command
set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_JPEG_CNTL), COND0, TYPE0, 0x6);
// wait for job completion, wait for job JBSI fetch done
set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_CTX_INDEX), COND0, TYPE0, 0x01C3);
set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE0, (dec->jpg.bsd_size >> 2));
set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_CTX_INDEX), COND0, TYPE0, 0x01C2);
set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE0, 0x01400200);
set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_JPEG_RB_RPTR), COND0, TYPE3, 0xFFFFFFFF);
// wait for job jpeg outbuf idle
set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_CTX_INDEX), COND0, TYPE0, 0x01C3);
set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE0, 0xFFFFFFFF);
set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_JPEG_OUTBUF_WPTR), COND0, TYPE3, 0x00000001);
// stop engine
set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_JPEG_CNTL), COND0, TYPE0, 0x4);
// asserting jpeg lmi drop
set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_CTX_INDEX), COND0, TYPE0, 0x0005);
set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE0, (1 << 23 | 1 << 0));
set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE1, 0);
// asserting jpeg reset
set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_JPEG_CNTL), COND0, TYPE0, 1);
// ensure reset is asserted in sclk domain
set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_CTX_INDEX), COND0, TYPE0, 0x01C3);
set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE0, (1 << 9));
set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_SOFT_RESET), COND0, TYPE3, (1 << 9));
// de-assert jpeg reset
set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_JPEG_CNTL), COND0, TYPE0, 0);
// ensure reset is de-asserted in sclk domain
set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_CTX_INDEX), COND0, TYPE0, 0x01C3);
set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE0, (0 << 9));
set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_SOFT_RESET), COND0, TYPE3, (1 << 9));
// de-asserting jpeg lmi drop
set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_CTX_INDEX), COND0, TYPE0, 0x0005);
set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE0, 0);
}
/* send a bitstream buffer command */
static void send_cmd_bitstream_direct(struct radeon_decoder *dec, struct pb_buffer_lean *buf,
uint32_t off, unsigned usage,
enum radeon_bo_domain domain)
{
uint64_t addr;
// jpeg soft reset
set_reg_jpeg(dec, dec->jpg_reg.jpeg_dec_soft_rst, COND0, TYPE0, 1);
// ensuring the Reset is asserted in SCLK domain
set_reg_jpeg(dec, dec->jpg_reg.jrbc_ib_cond_rd_timer, COND0, TYPE0, 0x01400200);
set_reg_jpeg(dec, dec->jpg_reg.jrbc_ib_ref_data, COND0, TYPE0, (0x1 << 0x10));
set_reg_jpeg(dec, dec->jpg_reg.jpeg_dec_soft_rst, COND3, TYPE3, (0x1 << 0x10));
// wait mem
set_reg_jpeg(dec, dec->jpg_reg.jpeg_dec_soft_rst, COND0, TYPE0, 0);
// ensuring the Reset is de-asserted in SCLK domain
set_reg_jpeg(dec, dec->jpg_reg.jrbc_ib_ref_data, COND0, TYPE0, (0 << 0x10));
set_reg_jpeg(dec, dec->jpg_reg.jpeg_dec_soft_rst, COND3, TYPE3, (0x1 << 0x10));
dec->ws->cs_add_buffer(&dec->jcs[dec->cb_idx], buf, usage | RADEON_USAGE_SYNCHRONIZED, domain);
addr = dec->ws->buffer_get_virtual_address(buf);
addr = addr + off;
// set UVD_LMI_JPEG_READ_64BIT_BAR_LOW/HIGH based on bitstream buffer address
set_reg_jpeg(dec, dec->jpg_reg.lmi_jpeg_read_64bit_bar_high, COND0, TYPE0, (addr >> 32));
set_reg_jpeg(dec, dec->jpg_reg.lmi_jpeg_read_64bit_bar_low, COND0, TYPE0, addr);
// set jpeg_rb_base
set_reg_jpeg(dec, dec->jpg_reg.jpeg_rb_base, COND0, TYPE0, 0);
// set jpeg_rb_base
set_reg_jpeg(dec, dec->jpg_reg.jpeg_rb_size, COND0, TYPE0, 0xFFFFFFF0);
// set jpeg_rb_wptr
set_reg_jpeg(dec, dec->jpg_reg.jpeg_rb_wptr, COND0, TYPE0, (dec->jpg.bsd_size >> 2));
}
/* send a target buffer command */
static void send_cmd_target_direct(struct radeon_decoder *dec, struct pb_buffer_lean *buf, uint32_t off,
unsigned usage, enum radeon_bo_domain domain,
enum pipe_format buffer_format)
{
uint64_t addr;
uint32_t val;
bool format_convert = false;
uint32_t fc_sps_info_val = 0;
switch (buffer_format) {
case PIPE_FORMAT_R8G8B8A8_UNORM:
format_convert = true;
fc_sps_info_val = 1 | (1 << 4) | (0xff << 8);
break;
case PIPE_FORMAT_A8R8G8B8_UNORM:
format_convert = true;
fc_sps_info_val = 1 | (1 << 4) | (1 << 5) | (0xff << 8);
break;
case PIPE_FORMAT_R8_G8_B8_UNORM:
format_convert = true;
fc_sps_info_val = 1 | (1 << 5) | (0xff << 8);
break;
default:
break;
}
if (dec->jpg_reg.version == RDECODE_JPEG_REG_VER_V3 && format_convert) {
set_reg_jpeg(dec, dec->jpg_reg.jpeg_pitch, COND0, TYPE0, dec->jpg.dt_pitch);
set_reg_jpeg(dec, dec->jpg_reg.jpeg_uv_pitch, COND0, TYPE0, dec->jpg.dt_uv_pitch);
} else {
set_reg_jpeg(dec, dec->jpg_reg.jpeg_pitch, COND0, TYPE0, (dec->jpg.dt_pitch >> 4));
set_reg_jpeg(dec, dec->jpg_reg.jpeg_uv_pitch, COND0, TYPE0, (dec->jpg.dt_uv_pitch >> 4));
}
set_reg_jpeg(dec, dec->jpg_reg.dec_addr_mode, COND0, TYPE0,
dec->jpg.dt_addr_mode | (dec->jpg.dt_addr_mode << 2));
set_reg_jpeg(dec, dec->jpg_reg.dec_y_gfx10_tiling_surface, COND0, TYPE0, dec->jpg.dt_swizzle_mode);
set_reg_jpeg(dec, dec->jpg_reg.dec_uv_gfx10_tiling_surface, COND0, TYPE0, dec->jpg.dt_swizzle_mode);
dec->ws->cs_add_buffer(&dec->jcs[dec->cb_idx], buf, usage | RADEON_USAGE_SYNCHRONIZED, domain);
addr = dec->ws->buffer_get_virtual_address(buf);
addr = addr + off;
// set UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW/HIGH based on target buffer address
set_reg_jpeg(dec, dec->jpg_reg.lmi_jpeg_write_64bit_bar_high, COND0, TYPE0, (addr >> 32));
set_reg_jpeg(dec, dec->jpg_reg.lmi_jpeg_write_64bit_bar_low, COND0, TYPE0, addr);
// set output buffer data address
if (dec->jpg_reg.version == RDECODE_JPEG_REG_VER_V2) {
set_reg_jpeg(dec, dec->jpg_reg.jpeg_index, COND0, TYPE0, 0);
set_reg_jpeg(dec, dec->jpg_reg.jpeg_data, COND0, TYPE0, dec->jpg.dt_luma_top_offset);
set_reg_jpeg(dec, dec->jpg_reg.jpeg_index, COND0, TYPE0, 1);
set_reg_jpeg(dec, dec->jpg_reg.jpeg_data, COND0, TYPE0, dec->jpg.dt_chroma_top_offset);
if (dec->jpg.dt_chromav_top_offset) {
set_reg_jpeg(dec, dec->jpg_reg.jpeg_index, COND0, TYPE0, 2);
set_reg_jpeg(dec, dec->jpg_reg.jpeg_data, COND0, TYPE0, dec->jpg.dt_chromav_top_offset);
}
} else {
set_reg_jpeg(dec, dec->jpg_reg.jpeg_luma_base0_0, COND0, TYPE0, dec->jpg.dt_luma_top_offset);
set_reg_jpeg(dec, dec->jpg_reg.jpeg_chroma_base0_0, COND0, TYPE0, dec->jpg.dt_chroma_top_offset);
set_reg_jpeg(dec, dec->jpg_reg.jpeg_chromav_base0_0, COND0, TYPE0, dec->jpg.dt_chromav_top_offset);
if (dec->jpg.crop_width && dec->jpg.crop_height) {
set_reg_jpeg(dec, vcnipUVD_JPEG_ROI_CROP_POS_START, COND0, TYPE0,
((dec->jpg.crop_y << 16) | dec->jpg.crop_x));
set_reg_jpeg(dec, vcnipUVD_JPEG_ROI_CROP_POS_STRIDE, COND0, TYPE0,
((dec->jpg.crop_height << 16) | dec->jpg.crop_width));
} else {
set_reg_jpeg(dec, vcnipUVD_JPEG_ROI_CROP_POS_START, COND0, TYPE0,
((0 << 16) | 0));
set_reg_jpeg(dec, vcnipUVD_JPEG_ROI_CROP_POS_STRIDE, COND0, TYPE0,
((1 << 16) | 1));
}
if (format_convert) {
/* set fc timeout control */
set_reg_jpeg(dec, vcnipUVD_JPEG_FC_TMEOUT_CNT, COND0, TYPE0,(4244373504));
/* set alpha position and packed format */
set_reg_jpeg(dec, vcnipUVD_JPEG_FC_SPS_INFO, COND0, TYPE0, fc_sps_info_val);
/* coefs */
set_reg_jpeg(dec, vcnipUVD_JPEG_FC_R_COEF, COND0, TYPE0, 256 | (0 << 10) | (403 << 20));
set_reg_jpeg(dec, vcnipUVD_JPEG_FC_G_COEF, COND0, TYPE0, 256 | (976 << 10) | (904 << 20));
set_reg_jpeg(dec, vcnipUVD_JPEG_FC_B_COEF, COND0, TYPE0, 256 | (475 << 10) | (0 << 20));
set_reg_jpeg(dec, vcnipUVD_JPEG_FC_VUP_COEF_CNTL0, COND0, TYPE0, 128 | (384 << 16));
set_reg_jpeg(dec, vcnipUVD_JPEG_FC_VUP_COEF_CNTL1, COND0, TYPE0, 384 | (128 << 16));
set_reg_jpeg(dec, vcnipUVD_JPEG_FC_VUP_COEF_CNTL2, COND0, TYPE0, 128 | (384 << 16));
set_reg_jpeg(dec, vcnipUVD_JPEG_FC_VUP_COEF_CNTL3, COND0, TYPE0, 384 | (128 << 16));
set_reg_jpeg(dec, vcnipUVD_JPEG_FC_HUP_COEF_CNTL0, COND0, TYPE0, 128 | (384 << 16));
set_reg_jpeg(dec, vcnipUVD_JPEG_FC_HUP_COEF_CNTL1, COND0, TYPE0, 384 | (128 << 16));
set_reg_jpeg(dec, vcnipUVD_JPEG_FC_HUP_COEF_CNTL2, COND0, TYPE0, 128 | (384 << 16));
set_reg_jpeg(dec, vcnipUVD_JPEG_FC_HUP_COEF_CNTL3, COND0, TYPE0, 384 | (128 << 16));
} else
set_reg_jpeg(dec, vcnipUVD_JPEG_FC_SPS_INFO, COND0, TYPE0, 1 | (1 << 5) | (255 << 8));
}
set_reg_jpeg(dec, dec->jpg_reg.jpeg_tier_cntl2, COND0, 0, 0);
// set output buffer read pointer
set_reg_jpeg(dec, dec->jpg_reg.jpeg_outbuf_rptr, COND0, TYPE0, 0);
set_reg_jpeg(dec, dec->jpg_reg.jpeg_outbuf_cntl, COND0, TYPE0,
((0x00001587 & (~0x00000180L)) | (0x1 << 0x7) | (0x1 << 0x6)));
// enable error interrupts
set_reg_jpeg(dec, dec->jpg_reg.jpeg_int_en, COND0, TYPE0, 0xFFFFFFFE);
// start engine command
val = 0x6;
if (dec->jpg_reg.version == RDECODE_JPEG_REG_VER_V3) {
if (dec->jpg.crop_width && dec->jpg.crop_height)
val = val | (0x1 << 24);
if (format_convert)
val = val | (1 << 16) | (1 << 18);
}
set_reg_jpeg(dec, dec->jpg_reg.jpeg_cntl, COND0, TYPE0, val);
// wait for job completion, wait for job JBSI fetch done
set_reg_jpeg(dec, dec->jpg_reg.jrbc_ib_ref_data, COND0, TYPE0, (dec->jpg.bsd_size >> 2));
set_reg_jpeg(dec, dec->jpg_reg.jrbc_ib_cond_rd_timer, COND0, TYPE0, 0x01400200);
set_reg_jpeg(dec, dec->jpg_reg.jpeg_rb_rptr, COND3, TYPE3, 0xFFFFFFFF);
// wait for job jpeg outbuf idle
set_reg_jpeg(dec, dec->jpg_reg.jrbc_ib_ref_data, COND0, TYPE0, 0xFFFFFFFF);
set_reg_jpeg(dec, dec->jpg_reg.jpeg_outbuf_wptr, COND3, TYPE3, 0x00000001);
if (dec->jpg_reg.version == RDECODE_JPEG_REG_VER_V3 && format_convert) {
val = val | (0x7 << 16);
set_reg_jpeg(dec, dec->jpg_reg.jrbc_ib_ref_data, COND0, TYPE0, 0);
set_reg_jpeg(dec, vcnipUVD_JPEG_INT_STAT, COND3, TYPE3, val);
}
// stop engine
set_reg_jpeg(dec, dec->jpg_reg.jpeg_cntl, COND0, TYPE0, 0x4);
}
/**
* send cmd for vcn jpeg
*/
bool send_cmd_jpeg(struct radeon_decoder *dec, struct pipe_video_buffer *target,
struct pipe_picture_desc *picture)
{
struct pb_buffer_lean *dt;
struct si_resource *bs_buf;
bs_buf = dec->bs_buffers[dec->cur_buffer];
memset(dec->bs_ptr, 0, align(dec->bs_size, 128) - dec->bs_size);
dec->ws->buffer_unmap(dec->ws, bs_buf->buf);
dec->bs_ptr = NULL;
dt = radeon_jpeg_get_decode_param(dec, target, picture);
if (dec->jpg_reg.version == RDECODE_JPEG_REG_VER_V1) {
send_cmd_bitstream(dec, bs_buf->buf, 0, RADEON_USAGE_READ, RADEON_DOMAIN_GTT);
send_cmd_target(dec, dt, 0, RADEON_USAGE_WRITE, RADEON_DOMAIN_VRAM);
} else {
send_cmd_bitstream_direct(dec, bs_buf->buf, 0, RADEON_USAGE_READ, RADEON_DOMAIN_GTT);
send_cmd_target_direct(dec, dt, 0, RADEON_USAGE_WRITE, RADEON_DOMAIN_VRAM, target->buffer_format);
}
return true;
}

1
src/gallium/drivers/radeonsi/si_pipe.c
View file

@ -8,7 +8,6 @@
#include "si_pipe.h"
#include "driver_ddebug/dd_util.h"
#include "radeon_uvd.h"
#include "si_public.h"
#include "sid.h"
#include "ac_shader_util.h"

16
src/gallium/drivers/radeonsi/si_uvd.c
View file

@ -7,10 +7,8 @@
**************************************************************************/
#include "drm-uapi/drm_fourcc.h"
#include "radeon_uvd.h"
#include "radeon_uvd_enc.h"
#include "radeon_vce.h"
#include "radeon_vcn_dec.h"
#include "radeon_vcn_enc.h"
#include "radeon_video.h"
#include "si_pipe.h"
@ -103,20 +101,6 @@ struct pipe_video_buffer *si_video_buffer_create(struct pipe_context *pipe,
return vl_video_buffer_create_as_resource(pipe, &vidbuf, modifiers, modifiers_count);
}
/* set the decoding target buffer offsets */
static struct pb_buffer_lean *si_uvd_set_dtb(struct ruvd_msg *msg, struct vl_video_buffer *buf)
{
struct si_screen *sscreen = (struct si_screen *)buf->base.context->screen;
struct si_texture *luma = (struct si_texture *)buf->resources[0];
struct si_texture *chroma = (struct si_texture *)buf->resources[1];
enum ruvd_surface_type type =
(sscreen->info.gfx_level >= GFX9) ? RUVD_SURFACE_TYPE_GFX9 : RUVD_SURFACE_TYPE_LEGACY;
si_uvd_set_dt_surfaces(msg, &luma->surface, (chroma) ? &chroma->surface : NULL, type);
return luma->buffer.buf;
}
/* get the radeon resources for VCE */
static void si_vce_get_buffer(struct pipe_resource *resource, struct pb_buffer_lean **handle,
struct radeon_surf **surface)