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anv/cmd_buffer: Unify flush_compute_state across gens
With one small genxml change, the two versions were basically identical. The only differences were one #define for HSW+ and a field that is missing on Haswell but exists everywhere else. Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
This commit is contained in:
Jason Ekstrand
parent
2314c9ed2e
commit
1f3e6468d2
5 changed files with 93 additions and 177 deletions
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@ -214,7 +214,7 @@
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</field>
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</field>
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<field name="Binding Table Pointer" start="133" end="143" type="offset"/>
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<field name="Binding Table Pointer" start="133" end="143" type="offset"/>
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<field name="Binding Table Entry Count" start="128" end="132" type="uint"/>
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<field name="Binding Table Entry Count" start="128" end="132" type="uint"/>
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<field name="Constant/Indirect URB Entry Read Length" start="176" end="191" type="uint"/>
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<field name="Constant URB Entry Read Length" start="176" end="191" type="uint"/>
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<field name="Constant URB Entry Read Offset" start="160" end="175" type="uint"/>
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<field name="Constant URB Entry Read Offset" start="160" end="175" type="uint"/>
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<field name="Rounding Mode" start="214" end="215" type="uint">
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<field name="Rounding Mode" start="214" end="215" type="uint">
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<value name="RTNE" value="0"/>
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<value name="RTNE" value="0"/>
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@ -203,7 +203,7 @@
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</field>
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</field>
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<field name="Binding Table Pointer" start="133" end="143" type="offset"/>
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<field name="Binding Table Pointer" start="133" end="143" type="offset"/>
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<field name="Binding Table Entry Count" start="128" end="132" type="uint"/>
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<field name="Binding Table Entry Count" start="128" end="132" type="uint"/>
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<field name="Constant/Indirect URB Entry Read Length" start="176" end="191" type="uint"/>
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<field name="Constant URB Entry Read Length" start="176" end="191" type="uint"/>
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<field name="Constant URB Entry Read Offset" start="160" end="175" type="uint"/>
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<field name="Constant URB Entry Read Offset" start="160" end="175" type="uint"/>
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<field name="Rounding Mode" start="214" end="215" type="uint">
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<field name="Rounding Mode" start="214" end="215" type="uint">
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<value name="RTNE" value="0"/>
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<value name="RTNE" value="0"/>
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@ -121,94 +121,6 @@ void genX(CmdBindIndexBuffer)(
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cmd_buffer->state.gen7.index_offset = offset;
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cmd_buffer->state.gen7.index_offset = offset;
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}
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}
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static VkResult
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flush_compute_descriptor_set(struct anv_cmd_buffer *cmd_buffer)
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{
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struct anv_device *device = cmd_buffer->device;
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struct anv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
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struct anv_state surfaces = { 0, }, samplers = { 0, };
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VkResult result;
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result = anv_cmd_buffer_emit_samplers(cmd_buffer,
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MESA_SHADER_COMPUTE, &samplers);
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if (result != VK_SUCCESS)
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return result;
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result = anv_cmd_buffer_emit_binding_table(cmd_buffer,
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MESA_SHADER_COMPUTE, &surfaces);
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if (result != VK_SUCCESS)
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return result;
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struct anv_state push_state = anv_cmd_buffer_cs_push_constants(cmd_buffer);
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const struct brw_cs_prog_data *cs_prog_data = get_cs_prog_data(pipeline);
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const struct brw_stage_prog_data *prog_data = &cs_prog_data->base;
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if (push_state.alloc_size) {
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anv_batch_emit(&cmd_buffer->batch, GENX(MEDIA_CURBE_LOAD), curbe) {
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curbe.CURBETotalDataLength = push_state.alloc_size;
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curbe.CURBEDataStartAddress = push_state.offset;
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}
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}
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const uint32_t slm_size = encode_slm_size(GEN_GEN, prog_data->total_shared);
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struct anv_state state =
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anv_state_pool_emit(&device->dynamic_state_pool,
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GENX(INTERFACE_DESCRIPTOR_DATA), 64,
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.KernelStartPointer = pipeline->cs_simd,
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.BindingTablePointer = surfaces.offset,
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.SamplerStatePointer = samplers.offset,
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.ConstantURBEntryReadLength =
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cs_prog_data->push.per_thread.regs,
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#if GEN_IS_HASWELL
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.CrossThreadConstantDataReadLength =
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cs_prog_data->push.cross_thread.regs,
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#else
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.ConstantURBEntryReadOffset = 0,
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#endif
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.BarrierEnable = cs_prog_data->uses_barrier,
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.SharedLocalMemorySize = slm_size,
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.NumberofThreadsinGPGPUThreadGroup =
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cs_prog_data->threads);
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const uint32_t size = GENX(INTERFACE_DESCRIPTOR_DATA_length) * sizeof(uint32_t);
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anv_batch_emit(&cmd_buffer->batch,
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GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD), idl) {
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idl.InterfaceDescriptorTotalLength = size;
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idl.InterfaceDescriptorDataStartAddress = state.offset;
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}
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return VK_SUCCESS;
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}
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void
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genX(cmd_buffer_flush_compute_state)(struct anv_cmd_buffer *cmd_buffer)
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{
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struct anv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
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MAYBE_UNUSED VkResult result;
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assert(pipeline->active_stages == VK_SHADER_STAGE_COMPUTE_BIT);
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genX(cmd_buffer_config_l3)(cmd_buffer, pipeline->urb.l3_config);
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genX(flush_pipeline_select_gpgpu)(cmd_buffer);
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if (cmd_buffer->state.compute_dirty & ANV_CMD_DIRTY_PIPELINE)
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anv_batch_emit_batch(&cmd_buffer->batch, &pipeline->batch);
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if ((cmd_buffer->state.descriptors_dirty & VK_SHADER_STAGE_COMPUTE_BIT) ||
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(cmd_buffer->state.compute_dirty & ANV_CMD_DIRTY_PIPELINE)) {
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/* FIXME: figure out descriptors for gen7 */
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result = flush_compute_descriptor_set(cmd_buffer);
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assert(result == VK_SUCCESS);
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cmd_buffer->state.descriptors_dirty &= ~VK_SHADER_STAGE_COMPUTE_BIT;
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}
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cmd_buffer->state.compute_dirty = 0;
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genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
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}
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void
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void
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genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
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genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
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{
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{
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@ -312,93 +312,6 @@ void genX(CmdBindIndexBuffer)(
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cmd_buffer->state.dirty |= ANV_CMD_DIRTY_INDEX_BUFFER;
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cmd_buffer->state.dirty |= ANV_CMD_DIRTY_INDEX_BUFFER;
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}
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}
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static VkResult
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flush_compute_descriptor_set(struct anv_cmd_buffer *cmd_buffer)
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{
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struct anv_device *device = cmd_buffer->device;
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struct anv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
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struct anv_state surfaces = { 0, }, samplers = { 0, };
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VkResult result;
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result = anv_cmd_buffer_emit_samplers(cmd_buffer,
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MESA_SHADER_COMPUTE, &samplers);
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if (result != VK_SUCCESS)
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return result;
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result = anv_cmd_buffer_emit_binding_table(cmd_buffer,
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MESA_SHADER_COMPUTE, &surfaces);
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if (result != VK_SUCCESS)
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return result;
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struct anv_state push_state = anv_cmd_buffer_cs_push_constants(cmd_buffer);
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const struct brw_cs_prog_data *cs_prog_data = get_cs_prog_data(pipeline);
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const struct brw_stage_prog_data *prog_data = &cs_prog_data->base;
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if (push_state.alloc_size) {
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anv_batch_emit(&cmd_buffer->batch, GENX(MEDIA_CURBE_LOAD), curbe) {
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curbe.CURBETotalDataLength = push_state.alloc_size;
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curbe.CURBEDataStartAddress = push_state.offset;
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}
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}
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const uint32_t slm_size = encode_slm_size(GEN_GEN, prog_data->total_shared);
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struct anv_state state =
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anv_state_pool_emit(&device->dynamic_state_pool,
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GENX(INTERFACE_DESCRIPTOR_DATA), 64,
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.KernelStartPointer = pipeline->cs_simd,
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.KernelStartPointerHigh = 0,
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.BindingTablePointer = surfaces.offset,
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.BindingTableEntryCount = 0,
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.SamplerStatePointer = samplers.offset,
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.SamplerCount = 0,
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.ConstantIndirectURBEntryReadLength =
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cs_prog_data->push.per_thread.regs,
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.ConstantURBEntryReadOffset = 0,
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.BarrierEnable = cs_prog_data->uses_barrier,
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.SharedLocalMemorySize = slm_size,
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.NumberofThreadsinGPGPUThreadGroup =
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cs_prog_data->threads,
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.CrossThreadConstantDataReadLength =
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cs_prog_data->push.cross_thread.regs);
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uint32_t size = GENX(INTERFACE_DESCRIPTOR_DATA_length) * sizeof(uint32_t);
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anv_batch_emit(&cmd_buffer->batch,
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GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD), mid) {
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mid.InterfaceDescriptorTotalLength = size;
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mid.InterfaceDescriptorDataStartAddress = state.offset;
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}
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return VK_SUCCESS;
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}
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void
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genX(cmd_buffer_flush_compute_state)(struct anv_cmd_buffer *cmd_buffer)
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{
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struct anv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
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MAYBE_UNUSED VkResult result;
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assert(pipeline->active_stages == VK_SHADER_STAGE_COMPUTE_BIT);
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genX(cmd_buffer_config_l3)(cmd_buffer, pipeline->urb.l3_config);
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genX(flush_pipeline_select_gpgpu)(cmd_buffer);
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if (cmd_buffer->state.compute_dirty & ANV_CMD_DIRTY_PIPELINE)
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anv_batch_emit_batch(&cmd_buffer->batch, &pipeline->batch);
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if ((cmd_buffer->state.descriptors_dirty & VK_SHADER_STAGE_COMPUTE_BIT) ||
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(cmd_buffer->state.compute_dirty & ANV_CMD_DIRTY_PIPELINE)) {
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result = flush_compute_descriptor_set(cmd_buffer);
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assert(result == VK_SUCCESS);
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cmd_buffer->state.descriptors_dirty &= ~VK_SHADER_STAGE_COMPUTE_BIT;
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}
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cmd_buffer->state.compute_dirty = 0;
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genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
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}
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/**
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/**
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* Emit the HZ_OP packet in the sequence specified by the BDW PRM section
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* Emit the HZ_OP packet in the sequence specified by the BDW PRM section
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@ -1022,6 +1022,97 @@ void genX(CmdDrawIndexedIndirect)(
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}
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}
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}
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}
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static VkResult
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flush_compute_descriptor_set(struct anv_cmd_buffer *cmd_buffer)
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{
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struct anv_device *device = cmd_buffer->device;
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struct anv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
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struct anv_state surfaces = { 0, }, samplers = { 0, };
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VkResult result;
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result = anv_cmd_buffer_emit_samplers(cmd_buffer,
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MESA_SHADER_COMPUTE, &samplers);
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if (result != VK_SUCCESS)
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return result;
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result = anv_cmd_buffer_emit_binding_table(cmd_buffer,
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MESA_SHADER_COMPUTE, &surfaces);
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if (result != VK_SUCCESS)
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return result;
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struct anv_state push_state = anv_cmd_buffer_cs_push_constants(cmd_buffer);
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const struct brw_cs_prog_data *cs_prog_data = get_cs_prog_data(pipeline);
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const struct brw_stage_prog_data *prog_data = &cs_prog_data->base;
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if (push_state.alloc_size) {
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anv_batch_emit(&cmd_buffer->batch, GENX(MEDIA_CURBE_LOAD), curbe) {
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curbe.CURBETotalDataLength = push_state.alloc_size;
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curbe.CURBEDataStartAddress = push_state.offset;
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}
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}
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const uint32_t slm_size = encode_slm_size(GEN_GEN, prog_data->total_shared);
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struct anv_state state =
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anv_state_pool_emit(&device->dynamic_state_pool,
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GENX(INTERFACE_DESCRIPTOR_DATA), 64,
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.KernelStartPointer = pipeline->cs_simd,
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.BindingTablePointer = surfaces.offset,
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.BindingTableEntryCount = 0,
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.SamplerStatePointer = samplers.offset,
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.SamplerCount = 0,
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#if !GEN_IS_HASWELL
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.ConstantURBEntryReadOffset = 0,
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#endif
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.ConstantURBEntryReadLength =
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cs_prog_data->push.per_thread.regs,
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#if GEN_GEN >= 8 || GEN_IS_HASWELL
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.CrossThreadConstantDataReadLength =
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cs_prog_data->push.cross_thread.regs,
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#endif
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.BarrierEnable = cs_prog_data->uses_barrier,
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.SharedLocalMemorySize = slm_size,
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.NumberofThreadsinGPGPUThreadGroup =
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cs_prog_data->threads);
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uint32_t size = GENX(INTERFACE_DESCRIPTOR_DATA_length) * sizeof(uint32_t);
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anv_batch_emit(&cmd_buffer->batch,
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GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD), mid) {
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mid.InterfaceDescriptorTotalLength = size;
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mid.InterfaceDescriptorDataStartAddress = state.offset;
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}
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return VK_SUCCESS;
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}
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void
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genX(cmd_buffer_flush_compute_state)(struct anv_cmd_buffer *cmd_buffer)
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{
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struct anv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
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MAYBE_UNUSED VkResult result;
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assert(pipeline->active_stages == VK_SHADER_STAGE_COMPUTE_BIT);
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genX(cmd_buffer_config_l3)(cmd_buffer, pipeline->urb.l3_config);
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genX(flush_pipeline_select_gpgpu)(cmd_buffer);
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if (cmd_buffer->state.compute_dirty & ANV_CMD_DIRTY_PIPELINE)
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anv_batch_emit_batch(&cmd_buffer->batch, &pipeline->batch);
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if ((cmd_buffer->state.descriptors_dirty & VK_SHADER_STAGE_COMPUTE_BIT) ||
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(cmd_buffer->state.compute_dirty & ANV_CMD_DIRTY_PIPELINE)) {
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/* FIXME: figure out descriptors for gen7 */
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result = flush_compute_descriptor_set(cmd_buffer);
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assert(result == VK_SUCCESS);
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cmd_buffer->state.descriptors_dirty &= ~VK_SHADER_STAGE_COMPUTE_BIT;
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}
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cmd_buffer->state.compute_dirty = 0;
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genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
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}
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#if GEN_GEN == 7
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#if GEN_GEN == 7
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static bool
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static bool
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