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intel/brw: Fix register and builder size in emit_barrier() for Xe2

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We were manually allocating 1 REG_SIZE for the barrier payload, which is
only half a register on Xe2.  This should eventually get allocated to a
whole register anyway, but it's awkward in the meantime.  Also, we were
zero-initializing the header using group(8, 0) which only initialized
half the register.  The rest of the fields are Reserved MBZ, so they're
likely unused and unread anyway - but it's better to zero-initialize
them so we don't get random undefined, miserable-to-debug behavior.

Backport-to: 24.2
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31499>
(cherry picked from commit dea61b7399)
This commit is contained in:
Kenneth Graunke 2024-10-02 14:24:17 -07:00 • committed by Eric Engestrom
parent 6fde580e83
commit 1f2d6b6aa2
2 changed files with 4 additions and 5 deletions
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2
.pick_status.json
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@ -354,7 +354,7 @@
"description": "intel/brw: Fix register and builder size in emit_barrier() for Xe2",
"nominated": true,
"nomination_type": 4,
"resolution": 0,
"resolution": 1,
"main_sha": null,
"because_sha": null,
"notes": null

7
src/intel/compiler/brw_fs_nir.cpp
View file

@ -2931,15 +2931,14 @@ emit_barrier(nir_to_brw_state &ntb)
const intel_device_info *devinfo = ntb.devinfo;
const fs_builder &bld = ntb.bld;
const fs_builder ubld = bld.exec_all();
const fs_builder hbld = ubld.group(8 * reg_unit(devinfo), 0);
fs_visitor &s = ntb.s;
/* We are getting the barrier ID from the compute shader header */
assert(gl_shader_stage_uses_workgroup(s.stage));
brw_reg payload = brw_vgrf(s.alloc.allocate(1), BRW_TYPE_UD);
/* Clear the message payload */
ubld.group(8, 0).MOV(payload, brw_imm_ud(0u));
/* Zero-initialize the payload */
brw_reg payload = hbld.MOV(brw_imm_ud(0u));
if (devinfo->verx10 >= 125) {
setup_barrier_message_payload_gfx125(bld, payload);