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i965: get rid of brw->can_do_pipelined_register_writes

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Instead, check the screen field directly.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Iago Toral Quiroga 2017-01-04 09:06:06 +01:00
parent 02a44484f0
commit 1f1b8def48
5 changed files with 10 additions and 10 deletions
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2
src/mesa/drivers/dri/i965/brw_context.c
View file

@ -983,8 +983,6 @@ brwCreateContext(gl_api api,
brw->must_use_separate_stencil = devinfo->must_use_separate_stencil;
brw->has_swizzling = screen->hw_has_swizzling;
brw->can_do_pipelined_register_writes =
screen->hw_has_pipelined_register & HW_HAS_PIPELINED_SOL_OFFSET;
isl_device_init(&brw->isl_dev, devinfo, screen->hw_has_swizzling);

5
src/mesa/drivers/dri/i965/brw_context.h
View file

@ -830,11 +830,6 @@ struct brw_context
bool use_rep_send;
bool use_resource_streamer;
/**
* Whether LRI can be used to write register values from the batch buffer.
*/
bool can_do_pipelined_register_writes;
/**
* Some versions of Gen hardware don't do centroid interpolation correctly
* on unlit pixels, causing incorrect values for derivatives near triangle

5
src/mesa/drivers/dri/i965/gen7_l3_state.c
View file

@ -229,7 +229,7 @@ emit_l3_state(struct brw_context *brw)
const float dw_threshold = (brw->ctx.NewDriverState & BRW_NEW_BATCH ?
small_dw_threshold : large_dw_threshold);
if (dw > dw_threshold && brw->can_do_pipelined_register_writes) {
if (dw > dw_threshold && can_do_pipelined_register_writes(brw->screen)) {
const struct gen_l3_config *const cfg =
gen_get_l3_config(&brw->screen->devinfo, w);
@ -296,7 +296,8 @@ gen7_restore_default_l3_config(struct brw_context *brw)
const struct gen_device_info *devinfo = &brw->screen->devinfo;
const struct gen_l3_config *const cfg = gen_get_default_l3_config(devinfo);
if (cfg != brw->l3.config && brw->can_do_pipelined_register_writes) {
if (cfg != brw->l3.config &&
can_do_pipelined_register_writes(brw->screen)) {
setup_l3_config(brw, cfg);
update_urb_size(brw, cfg);
brw->l3.config = cfg;

2
src/mesa/drivers/dri/i965/intel_extensions.c
View file

@ -219,7 +219,7 @@ intelInitExtensions(struct gl_context *ctx)
if (brw->is_haswell)
ctx->Extensions.ARB_gpu_shader_fp64 = true;
if (brw->can_do_pipelined_register_writes) {
if (can_do_pipelined_register_writes(brw->screen)) {
ctx->Extensions.ARB_draw_indirect = true;
ctx->Extensions.ARB_transform_feedback2 = true;
ctx->Extensions.ARB_transform_feedback3 = true;

6
src/mesa/drivers/dri/i965/intel_screen.h
View file

@ -127,4 +127,10 @@ void aub_dump_bmp(struct gl_context *ctx);
const int*
intel_supported_msaa_modes(const struct intel_screen *screen);
static inline bool
can_do_pipelined_register_writes(const struct intel_screen *screen)
{
return screen->hw_has_pipelined_register & HW_HAS_PIPELINED_SOL_OFFSET;
}
#endif