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i965/gen7: Align all depth miplevels to 8 in the X direction.

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On an INTEL_DEBUG=perf piglit run on IVB, reduces the instances of "HW
workaround: blit" (the printouts from the misaligned-depth workaround
blits) from 725 to 675.

It doesn't totally eliminate the workaround blit, because we still have
problems with Y offsets that we can't fix (since texturing can only align
miplevels up to 2 or 4, not 8).

No regressions on piglit/es3conform on IVB.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Eric Anholt 2013-03-18 15:38:58 -07:00
parent 529dbbfcf7
commit 1f112ccf02
1 changed files with 9 additions and 1 deletions
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10
src/mesa/drivers/dri/intel/intel_tex_layout.c
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@ -77,7 +77,15 @@ intel_horizontal_texture_alignment_unit(struct intel_context *intel,
if (format == MESA_FORMAT_S8)
return 8;
if (intel->gen >= 7 && format == MESA_FORMAT_Z16)
/* The depth alignment requirements in the table above are for rendering to
* depth miplevels using the LOD control fields. We don't use LOD control
* fields, and instead use page offsets plus intra-tile x/y offsets, which
* require that the low 3 bits are zero. To reduce the number of x/y
* offset workaround blits we do, align the X to 8, which depth texturing
* can handle (sadly, it can't handle 8 in the Y direction).
*/
if (intel->gen >= 7 &&
_mesa_get_format_base_format(format) == GL_DEPTH_COMPONENT)
return 8;
return 4;