From 1f083e183960af0f3e0ecf7df793fdb6c643aada Mon Sep 17 00:00:00 2001 From: Kenneth Graunke Date: Mon, 26 Sep 2011 23:57:40 -0700 Subject: [PATCH] i965: Allow SIMD16 color writes on Ivybridge. Again, the check was needlessly specific: this works fine on Gen7. Signed-off-by: Kenneth Graunke Reviewed-by: Eric Anholt (cherry picked from commit 7db874bf4c4273d2d46218b1490d312fe2654284) --- src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp index e727634e0ca..94541e0ae3f 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp @@ -1739,7 +1739,7 @@ fs_visitor::emit_color_write(int index, int first_color_mrf, fs_reg color) int reg_width = c->dispatch_width / 8; fs_inst *inst; - if (c->dispatch_width == 8 || intel->gen == 6) { + if (c->dispatch_width == 8 || intel->gen >= 6) { /* SIMD8 write looks like: * m + 0: r0 * m + 1: r1