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freedreno/ir3: fix # of registers

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The instruction encoding allows for more registers, but at least on
a3xx/a4xx they don't actually exist.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
This commit is contained in:
Rob Clark 2016-04-30 13:47:04 -04:00
parent 173871dfb9
commit 1f04d4bf59
1 changed files with 1 additions and 1 deletions
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src/gallium/drivers/freedreno/ir3/ir3_ra.c
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@ -98,7 +98,7 @@ static const unsigned half_class_sizes[] = {
#define total_class_count (class_count + half_class_count)
/* Below a0.x are normal regs. RA doesn't need to assign a0.x/p0.x. */
#define NUM_REGS (4 * (REG_A0 - 1))
#define NUM_REGS (4 * 48)
/* Number of virtual regs in a given class: */
#define CLASS_REGS(i) (NUM_REGS - (class_sizes[i] - 1))
#define HALF_CLASS_REGS(i) (NUM_REGS - (half_class_sizes[i] - 1))