diff --git a/src/freedreno/ir3/ir3.c b/src/freedreno/ir3/ir3.c index 1b5908c8b57..d266805b757 100644 --- a/src/freedreno/ir3/ir3.c +++ b/src/freedreno/ir3/ir3.c @@ -125,6 +125,7 @@ ir3_should_double_threadsize(struct ir3_shader_variant *v, unsigned regs_count) } switch (v->type) { + case MESA_SHADER_KERNEL: case MESA_SHADER_COMPUTE: { unsigned threads_per_wg = v->local_size[0] * v->local_size[1] * v->local_size[2]; @@ -177,7 +178,8 @@ ir3_get_reg_independent_max_waves(struct ir3_shader_variant *v, unsigned max_waves = compiler->max_waves; /* If this is a compute shader, compute the limit based on shared size */ - if (v->type == MESA_SHADER_COMPUTE) { + if ((v->type == MESA_SHADER_COMPUTE) || + (v->type == MESA_SHADER_KERNEL)) { /* Shared is allocated in chunks of 1k */ unsigned shared_per_wg = ALIGN_POT(v->shared_size, 1024); if (shared_per_wg > 0 && !v->local_size_variable) { diff --git a/src/freedreno/ir3/ir3_compiler.h b/src/freedreno/ir3/ir3_compiler.h index 0a13f0465df..1fb6046d340 100644 --- a/src/freedreno/ir3/ir3_compiler.h +++ b/src/freedreno/ir3/ir3_compiler.h @@ -228,6 +228,7 @@ shader_debug_enabled(gl_shader_stage type) case MESA_SHADER_FRAGMENT: return !!(ir3_shader_debug & IR3_DBG_SHADER_FS); case MESA_SHADER_COMPUTE: + case MESA_SHADER_KERNEL: return !!(ir3_shader_debug & IR3_DBG_SHADER_CS); default: debug_assert(0); diff --git a/src/freedreno/ir3/ir3_compiler_nir.c b/src/freedreno/ir3/ir3_compiler_nir.c index 0a7e00c0f71..8ca00c8dc76 100644 --- a/src/freedreno/ir3/ir3_compiler_nir.c +++ b/src/freedreno/ir3/ir3_compiler_nir.c @@ -3680,6 +3680,7 @@ uses_store_output(struct ir3_shader_variant *so) return true; case MESA_SHADER_TESS_CTRL: case MESA_SHADER_COMPUTE: + case MESA_SHADER_KERNEL: return false; default: unreachable("unknown stage"); diff --git a/src/freedreno/ir3/ir3_nir.c b/src/freedreno/ir3/ir3_nir.c index a630b0585a8..85f5048a1be 100644 --- a/src/freedreno/ir3/ir3_nir.c +++ b/src/freedreno/ir3/ir3_nir.c @@ -232,7 +232,8 @@ ir3_optimize_loop(struct ir3_compiler *compiler, nir_shader *s) * for other stages. */ if ((s->info.stage == MESA_SHADER_FRAGMENT) || - (s->info.stage == MESA_SHADER_COMPUTE)) { + (s->info.stage == MESA_SHADER_COMPUTE) || + (s->info.stage == MESA_SHADER_KERNEL)) { progress |= OPT(s, nir_opt_phi_precision); } progress |= OPT(s, nir_opt_algebraic); @@ -531,7 +532,8 @@ ir3_nir_post_finalize(struct ir3_compiler *compiler, nir_shader *s) NIR_PASS_V(s, nir_lower_mediump_io, nir_var_shader_out, 0, false); } - if (s->info.stage == MESA_SHADER_COMPUTE) { + if ((s->info.stage == MESA_SHADER_COMPUTE) || + (s->info.stage == MESA_SHADER_KERNEL)) { bool progress = false; NIR_PASS(progress, s, nir_lower_subgroups, &(nir_lower_subgroups_options){ diff --git a/src/freedreno/ir3/ir3_shader.c b/src/freedreno/ir3/ir3_shader.c index c6a7986fced..f2b5afbb0dc 100644 --- a/src/freedreno/ir3/ir3_shader.c +++ b/src/freedreno/ir3/ir3_shader.c @@ -183,7 +183,8 @@ ir3_shader_assemble(struct ir3_shader_variant *v) * index. */ v->pvtmem_per_wave = compiler->gen >= 6 && !info->multi_dword_ldp_stp && - v->type == MESA_SHADER_COMPUTE; + ((v->type == MESA_SHADER_COMPUTE) || + (v->type == MESA_SHADER_KERNEL)); fixup_regfootprint(v); diff --git a/src/freedreno/ir3/ir3_shader.h b/src/freedreno/ir3/ir3_shader.h index 3337b6252e5..26af7f21979 100644 --- a/src/freedreno/ir3/ir3_shader.h +++ b/src/freedreno/ir3/ir3_shader.h @@ -695,6 +695,7 @@ ir3_shader_stage(struct ir3_shader_variant *v) case MESA_SHADER_FRAGMENT: return "FRAG"; case MESA_SHADER_COMPUTE: + case MESA_SHADER_KERNEL: return "CL"; default: unreachable("invalid type"); @@ -770,7 +771,8 @@ ir3_max_const(const struct ir3_shader_variant *v) { const struct ir3_compiler *compiler = v->shader->compiler; - if (v->shader->type == MESA_SHADER_COMPUTE) { + if ((v->shader->type == MESA_SHADER_COMPUTE) || + (v->shader->type == MESA_SHADER_KERNEL)) { return compiler->max_const_compute; } else if (v->key.safe_constlen) { return compiler->max_const_safe;