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anv: Advertise only OUTPUT_COINCIDE_BIT for AV1 video decoding

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Intel HW does not support separate destination and reference output pictures
when decoding AV1 video. The only exception is film grain, which the Vulkan
spec already includes a caveat for.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37351>
This commit is contained in:
Calder Young 2025-09-16 13:36:08 -07:00 • committed by Marge Bot
parent f952e27d6e
commit 1e8b96c40c
2 changed files with 9 additions and 10 deletions
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1
src/intel/vulkan/anv_video.c
View file

@ -139,7 +139,6 @@ anv_GetPhysicalDeviceVideoCapabilitiesKHR(VkPhysicalDevice physicalDevice,
pCapabilities->maxDpbSlots = STD_VIDEO_AV1_NUM_REF_FRAMES + 1;
pCapabilities->maxActiveReferencePictures = STD_VIDEO_AV1_NUM_REF_FRAMES;
dec_caps->flags |= VK_VIDEO_DECODE_CAPABILITY_DPB_AND_OUTPUT_DISTINCT_BIT_KHR;
strcpy(pCapabilities->stdHeaderVersion.extensionName, VK_STD_VULKAN_VIDEO_CODEC_AV1_DECODE_EXTENSION_NAME);
pCapabilities->stdHeaderVersion.specVersion = VK_STD_VULKAN_VIDEO_CODEC_AV1_DECODE_SPEC_VERSION;

18
src/intel/vulkan/genX_cmd_video.c
View file

@ -1486,9 +1486,9 @@ anv_av1_decode_video_tile(struct anv_cmd_buffer *cmd_buffer,
anv_batch_emit(&cmd_buffer->batch, GENX(AVP_SURFACE_STATE), ss) {
ss.SurfaceFormat = is_10bit ? AVP_P010 : AVP_PLANAR_420_8;
ss.SurfacePitchMinus1 = dst_img->planes[0].primary_surface.isl.row_pitch_B - 1;
ss.YOffsetforUCb = dst_img->planes[1].primary_surface.memory_range.offset /
dst_img->planes[0].primary_surface.isl.row_pitch_B;
ss.SurfacePitchMinus1 = dpb_img->planes[0].primary_surface.isl.row_pitch_B - 1;
ss.YOffsetforUCb = dpb_img->planes[1].primary_surface.memory_range.offset /
dpb_img->planes[0].primary_surface.isl.row_pitch_B;
};
if (!frame_is_key_or_intra(std_pic_info->frame_type)) {
@ -1509,9 +1509,9 @@ anv_av1_decode_video_tile(struct anv_cmd_buffer *cmd_buffer,
anv_batch_emit(&cmd_buffer->batch, GENX(AVP_SURFACE_STATE), ss) {
ss.SurfaceID = 0xE;
ss.SurfaceFormat = is_10bit ? AVP_P010 : AVP_PLANAR_420_8;
ss.SurfacePitchMinus1 = dst_img->planes[0].primary_surface.isl.row_pitch_B - 1;
ss.YOffsetforUCb = dst_img->planes[1].primary_surface.memory_range.offset /
dst_img->planes[0].primary_surface.isl.row_pitch_B;
ss.SurfacePitchMinus1 = dpb_img->planes[0].primary_surface.isl.row_pitch_B - 1;
ss.YOffsetforUCb = dpb_img->planes[1].primary_surface.memory_range.offset /
dpb_img->planes[0].primary_surface.isl.row_pitch_B;
}
}
@ -1522,11 +1522,11 @@ anv_av1_decode_video_tile(struct anv_cmd_buffer *cmd_buffer,
#endif
anv_batch_emit(&cmd_buffer->batch, GENX(AVP_PIPE_BUF_ADDR_STATE), buf) {
buf.DecodedOutputFrameBufferAddress =
anv_image_dpb_address(dst_iv, frame_info->dstPictureResource.baseArrayLayer);
anv_image_dpb_address(dpb_iv, dpb_array_layer);
buf.DecodedOutputFrameBufferAddressAttributes = (struct GENX(MEMORYADDRESSATTRIBUTES)) {
.MOCS = anv_mocs(cmd_buffer->device, buf.DecodedOutputFrameBufferAddress.bo, 0),
#if GFX_VERx10 >= 125
.TiledResourceMode = TRMODE_TILEF,
.TiledResourceMode = TRMODE_TILEF,
#endif
};
buf.CurrentFrameMVWriteBufferAddress =
@ -1537,7 +1537,7 @@ anv_av1_decode_video_tile(struct anv_cmd_buffer *cmd_buffer,
if (std_pic_info->flags.allow_intrabc) {
buf.IntraBCDecodedOutputFrameBufferAddress =
anv_image_dpb_address(dst_iv, frame_info->dstPictureResource.baseArrayLayer);
anv_image_dpb_address(dpb_iv, dpb_array_layer);
}
buf.IntraBCDecodedOutputFrameBufferAddressAttributes = (struct GENX(MEMORYADDRESSATTRIBUTES)) {