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pvr: feature promotion to core from derived
RGX_FEATURE_USC_ITR_PARALLEL_INSTANCES is no longer a derived feature for Volcanic, it is a core feature. This improvement is related to the introduction of Volcanic device information. Signed-off-by: leonperianu <leon.perianu@imgtec.com> Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38423>
This commit is contained in:
parent
bf1d9d1339
commit
1e548195d2
11 changed files with 25 additions and 36 deletions
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@ -62,6 +62,7 @@ static const struct pvr_device_features pvr_device_features_33_V_11_3 = {
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.has_tpu_parallel_instances = true,
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.has_unified_store_depth = true,
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.has_usc_f16sop_u8 = true,
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.has_usc_itr_parallel_instances = true,
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.has_usc_min_output_registers_per_pix = true,
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.has_usc_pixel_partition_mask = true,
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.has_usc_slots = true,
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@ -86,6 +87,7 @@ static const struct pvr_device_features pvr_device_features_33_V_11_3 = {
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.tile_size_y = 16U,
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.tpu_parallel_instances = 1U,
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.unified_store_depth = 64U,
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.usc_itr_parallel_instances = 4U,
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.usc_min_output_registers_per_pix = 1U,
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.usc_slots = 14U,
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.uvs_banks = 2U,
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@ -94,9 +96,6 @@ static const struct pvr_device_features pvr_device_features_33_V_11_3 = {
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.vdm_cam_size = 32U,
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.has_s8xe = true,
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.has_usc_itr_parallel_instances = true,
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.usc_itr_parallel_instances = 4U,
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};
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static const struct pvr_device_enhancements pvr_device_enhancements_33_15_11_3 = {
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@ -53,6 +53,8 @@ static const struct pvr_device_features pvr_device_features_36_V_52_182 = {
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.has_usc_f16sop_u8 = true,
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.has_usc_itrsmp = true,
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.has_usc_itrsmp_enhanced = true,
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.has_usc_itr_parallel_instances = true,
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.has_usc_min_output_registers_per_pix = true,
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.has_usc_pixel_partition_mask = true,
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.has_usc_slots = true,
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@ -78,6 +80,7 @@ static const struct pvr_device_features pvr_device_features_36_V_52_182 = {
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.tile_size_y = 16U,
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.tpu_parallel_instances = 2U,
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.unified_store_depth = 128U,
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.usc_itr_parallel_instances = 8U,
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.usc_min_output_registers_per_pix = 2U,
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.usc_slots = 32U,
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.uvs_banks = 4U,
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@ -87,9 +90,6 @@ static const struct pvr_device_features pvr_device_features_36_V_52_182 = {
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.xpu_max_slaves = 3U,
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.has_s8xe = true,
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.has_usc_itr_parallel_instances = true,
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.usc_itr_parallel_instances = 8U,
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};
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static const struct pvr_device_enhancements
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@ -54,6 +54,7 @@ static const struct pvr_device_features pvr_device_features_36_V_54_182 = {
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.has_usc_itrsmp = true,
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.has_usc_itrsmp_enhanced = true,
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.has_usc_f16sop_u8 = true,
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.has_usc_itr_parallel_instances = true,
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.has_usc_min_output_registers_per_pix = true,
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.has_usc_pixel_partition_mask = true,
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.has_usc_slots = true,
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@ -79,6 +80,7 @@ static const struct pvr_device_features pvr_device_features_36_V_54_182 = {
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.tile_size_y = 16U,
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.tpu_parallel_instances = 4U,
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.unified_store_depth = 208U,
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.usc_itr_parallel_instances = 16U,
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.usc_min_output_registers_per_pix = 2U,
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.usc_slots = 64U,
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.uvs_banks = 8U,
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@ -88,9 +90,6 @@ static const struct pvr_device_features pvr_device_features_36_V_54_182 = {
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.xpu_max_slaves = 3U,
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.has_s8xe = true,
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.has_usc_itr_parallel_instances = true,
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.usc_itr_parallel_instances = 16U,
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};
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static const struct pvr_device_enhancements
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@ -54,6 +54,7 @@ static const struct pvr_device_features pvr_device_features_36_V_104_182 = {
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.has_usc_f16sop_u8 = true,
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.has_usc_itrsmp = true,
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.has_usc_itrsmp_enhanced = true,
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.has_usc_itr_parallel_instances = true,
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.has_usc_min_output_registers_per_pix = true,
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.has_usc_pixel_partition_mask = true,
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.has_usc_slots = true,
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@ -79,6 +80,7 @@ static const struct pvr_device_features pvr_device_features_36_V_104_182 = {
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.tile_size_y = 16U,
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.tpu_parallel_instances = 4U,
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.unified_store_depth = 256U,
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.usc_itr_parallel_instances = 16U,
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.usc_min_output_registers_per_pix = 2U,
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.usc_slots = 64U,
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.uvs_banks = 8U,
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@ -89,9 +91,6 @@ static const struct pvr_device_features pvr_device_features_36_V_104_182 = {
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/* Derived features. */
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.has_s8xe = true,
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.has_usc_itr_parallel_instances = true,
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.usc_itr_parallel_instances = 16U,
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};
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static const struct pvr_device_enhancements
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@ -72,6 +72,7 @@ static const struct pvr_device_features pvr_device_features_36_V_104_796 = {
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.has_usc_f16sop_u8 = true,
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.has_usc_itrsmp = true,
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.has_usc_itrsmp_enhanced = true,
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.has_usc_itr_parallel_instances = true,
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.has_usc_min_output_registers_per_pix = true,
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.has_usc_pixel_partition_mask = true,
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.has_usc_slots = true,
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@ -98,6 +99,7 @@ static const struct pvr_device_features pvr_device_features_36_V_104_796 = {
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.tile_size_y = 16U,
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.tpu_parallel_instances = 4U,
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.unified_store_depth = 256U,
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.usc_itr_parallel_instances = 16U,
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.usc_min_output_registers_per_pix = 2U,
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.usc_slots = 64U,
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.uvs_banks = 8U,
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@ -107,9 +109,6 @@ static const struct pvr_device_features pvr_device_features_36_V_104_796 = {
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.xpu_max_slaves = 3U,
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.has_s8xe = true,
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.has_usc_itr_parallel_instances = true,
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.usc_itr_parallel_instances = 16U,
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};
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static const struct pvr_device_enhancements
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@ -34,6 +34,7 @@ static const struct pvr_device_features pvr_device_features_5_V_1_46 = {
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.has_tile_size_y = true,
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.has_tpu_parallel_instances = true,
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.has_unified_store_depth = true,
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.has_usc_itr_parallel_instances = true,
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.has_usc_min_output_registers_per_pix = true,
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.has_usc_slots = true,
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.has_uvs_banks = true,
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@ -56,6 +57,7 @@ static const struct pvr_device_features pvr_device_features_5_V_1_46 = {
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.tile_size_y = 32U,
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.tpu_parallel_instances = 4U,
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.unified_store_depth = 208U,
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.usc_itr_parallel_instances = 16U,
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.usc_min_output_registers_per_pix = 2U,
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.usc_slots = 56U,
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.uvs_banks = 8U,
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@ -64,9 +66,6 @@ static const struct pvr_device_features pvr_device_features_5_V_1_46 = {
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.vdm_cam_size = 64U,
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.has_requires_fb_cdc_zls_setup = true,
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.has_usc_itr_parallel_instances = true,
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.usc_itr_parallel_instances = 16U,
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};
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static const struct pvr_device_enhancements pvr_device_enhancements_5_9_1_46 = {
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@ -36,6 +36,7 @@ static const struct pvr_device_features pvr_device_features_15_V_1_64 = {
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.has_tpu_parallel_instances = true,
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.has_unified_store_depth = true,
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.has_usc_f16sop_u8 = true,
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.has_usc_itr_parallel_instances = true,
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.has_usc_min_output_registers_per_pix = true,
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.has_usc_slots = true,
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.has_uvs_banks = true,
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@ -58,6 +59,7 @@ static const struct pvr_device_features pvr_device_features_15_V_1_64 = {
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.tile_size_y = 32U,
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.tpu_parallel_instances = 4U,
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.unified_store_depth = 208U,
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.usc_itr_parallel_instances = 16U,
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.usc_min_output_registers_per_pix = 2U,
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.usc_slots = 56U,
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.uvs_banks = 8U,
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@ -66,9 +68,6 @@ static const struct pvr_device_features pvr_device_features_15_V_1_64 = {
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.vdm_cam_size = 128U,
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.has_requires_fb_cdc_zls_setup = true,
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.has_usc_itr_parallel_instances = true,
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.usc_itr_parallel_instances = 16U,
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};
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static const struct pvr_device_enhancements
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@ -45,6 +45,7 @@ static const struct pvr_device_features pvr_device_features_22_V_54_30 = {
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.has_usc_f16sop_u8 = true,
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.has_usc_itrsmp = true,
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.has_usc_itrsmp_enhanced = true,
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.has_usc_itr_parallel_instances = true,
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.has_usc_min_output_registers_per_pix = true,
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.has_usc_slots = true,
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.has_uvs_banks = true,
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@ -67,6 +68,7 @@ static const struct pvr_device_features pvr_device_features_22_V_54_30 = {
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.tile_size_y = 16U,
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.tpu_parallel_instances = 4U,
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.unified_store_depth = 208U,
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.usc_itr_parallel_instances = 16U,
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.usc_min_output_registers_per_pix = 2U,
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.usc_slots = 64U,
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.uvs_banks = 4U,
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@ -75,9 +77,6 @@ static const struct pvr_device_features pvr_device_features_22_V_54_30 = {
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.vdm_cam_size = 64U,
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.has_s8xe = true,
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.has_usc_itr_parallel_instances = true,
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.usc_itr_parallel_instances = 16U,
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};
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static const struct pvr_device_enhancements
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@ -63,6 +63,7 @@ static const struct pvr_device_features pvr_device_features_4_V_2_51 = {
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.has_unified_store_depth = true,
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.has_usc_f16sop_u8 = true,
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.has_usc_itrsmp = true,
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.has_usc_itr_parallel_instances = true,
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.has_usc_min_output_registers_per_pix = true,
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.has_usc_slots = true,
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.has_uvs_banks = true,
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@ -87,6 +88,7 @@ static const struct pvr_device_features pvr_device_features_4_V_2_51 = {
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.tile_size_y = 32U,
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.tpu_parallel_instances = 4U,
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.unified_store_depth = 256U,
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.usc_itr_parallel_instances = 8U,
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.usc_min_output_registers_per_pix = 2U,
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.usc_slots = 32U,
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.uvs_banks = 8U,
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@ -95,9 +97,6 @@ static const struct pvr_device_features pvr_device_features_4_V_2_51 = {
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.vdm_cam_size = 256U,
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.has_requires_fb_cdc_zls_setup = true,
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.has_usc_itr_parallel_instances = true,
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.usc_itr_parallel_instances = 8U,
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};
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static const struct pvr_device_enhancements pvr_device_enhancements_4_40_2_51 = {
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@ -175,6 +174,7 @@ static const struct pvr_device_features pvr_device_features_4_V_2_58 = {
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.has_unified_store_depth = true,
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.has_usc_f16sop_u8 = true,
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.has_usc_itrsmp = true,
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.has_usc_itr_parallel_instances = true,
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.has_usc_min_output_registers_per_pix = true,
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.has_usc_slots = true,
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.has_uvs_banks = true,
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@ -199,6 +199,7 @@ static const struct pvr_device_features pvr_device_features_4_V_2_58 = {
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.tile_size_y = 32U,
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.tpu_parallel_instances = 4U,
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.unified_store_depth = 256U,
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.usc_itr_parallel_instances = 8U,
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.usc_min_output_registers_per_pix = 2U,
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.usc_slots = 32U,
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.uvs_banks = 8U,
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@ -207,9 +208,6 @@ static const struct pvr_device_features pvr_device_features_4_V_2_58 = {
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.vdm_cam_size = 256U,
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.has_requires_fb_cdc_zls_setup = true,
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.has_usc_itr_parallel_instances = true,
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.usc_itr_parallel_instances = 8U,
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};
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static const struct pvr_device_enhancements pvr_device_enhancements_4_45_2_58 = {
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@ -46,6 +46,7 @@ static const struct pvr_device_features pvr_device_features_4_V_6_62 = {
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.has_unified_store_depth = true,
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.has_usc_f16sop_u8 = true,
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.has_usc_itrsmp = true,
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.has_usc_itr_parallel_instances = true,
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.has_usc_min_output_registers_per_pix = true,
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.has_usc_slots = true,
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.has_uvs_banks = true,
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@ -70,6 +71,7 @@ static const struct pvr_device_features pvr_device_features_4_V_6_62 = {
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.tile_size_y = 32U,
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.tpu_parallel_instances = 4U,
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.unified_store_depth = 256U,
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.usc_itr_parallel_instances = 8U,
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.usc_min_output_registers_per_pix = 2U,
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.usc_slots = 32U,
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.uvs_banks = 8U,
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@ -78,9 +80,6 @@ static const struct pvr_device_features pvr_device_features_4_V_6_62 = {
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.vdm_cam_size = 256U,
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.has_requires_fb_cdc_zls_setup = true,
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.has_usc_itr_parallel_instances = true,
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.usc_itr_parallel_instances = 8U,
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};
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static const struct pvr_device_enhancements pvr_device_enhancements_4_46_6_62 = {
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@ -297,6 +297,7 @@ struct pvr_device_features {
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bool has_usc_f16sop_u8 : 1;
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bool has_usc_itrsmp : 1;
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bool has_usc_itrsmp_enhanced : 1;
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bool has_usc_itr_parallel_instances : 1;
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bool has_usc_min_output_registers_per_pix : 1;
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bool has_usc_pixel_partition_mask : 1;
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bool has_usc_slots : 1;
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@ -325,6 +326,7 @@ struct pvr_device_features {
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uint32_t tile_size_y;
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uint32_t tpu_parallel_instances;
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uint32_t unified_store_depth;
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uint32_t usc_itr_parallel_instances;
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uint32_t usc_min_output_registers_per_pix;
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uint32_t usc_slots;
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uint32_t uvs_banks;
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@ -336,9 +338,6 @@ struct pvr_device_features {
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/* Derived features. */
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bool has_requires_fb_cdc_zls_setup : 1;
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bool has_s8xe : 1;
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bool has_usc_itr_parallel_instances : 1;
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uint32_t usc_itr_parallel_instances;
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};
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struct pvr_device_enhancements {
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