fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-05-09 11:08:03 +02:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

etnaviv: blend: Store information per render target

Browse source 
This is a prep change to add MRT support.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26565>
This commit is contained in:
Christian Gmeiner 2023-11-20 14:31:02 +01:00 • committed by Marge Bot
parent c9158f5aab
commit 1e4ad853df
3 changed files with 15 additions and 12 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

10
src/gallium/drivers/etnaviv/etnaviv_blend.c
View file

@ -78,7 +78,7 @@ etna_blend_state_create(struct pipe_context *pctx,
rt0->rgb_func == rt0->alpha_func);
if (alpha_enable) {
co->PE_ALPHA_CONFIG =
co->rt[0].PE_ALPHA_CONFIG =
VIVS_PE_ALPHA_CONFIG_BLEND_ENABLE_COLOR |
COND(separate_alpha, VIVS_PE_ALPHA_CONFIG_BLEND_SEPARATE_ALPHA) |
VIVS_PE_ALPHA_CONFIG_SRC_FUNC_COLOR(translate_blend_factor(rt0->rgb_src_factor)) |
@ -88,7 +88,7 @@ etna_blend_state_create(struct pipe_context *pctx,
VIVS_PE_ALPHA_CONFIG_EQ_COLOR(rt0->rgb_func) |
VIVS_PE_ALPHA_CONFIG_EQ_ALPHA(rt0->alpha_func);
} else {
co->PE_ALPHA_CONFIG = 0;
co->rt[0].PE_ALPHA_CONFIG = 0;
}
logicop_enable = so->logicop_enable &&
@ -99,7 +99,7 @@ etna_blend_state_create(struct pipe_context *pctx,
VIVS_PE_LOGIC_OP_DITHER_MODE(3) | /* TODO: related to dithering, sometimes 2 */
0x000E4000 /* ??? */;
co->fo_allowed = !alpha_enable && !logicop_enable;
co->rt[0].fo_allowed = !alpha_enable && !logicop_enable;
/* independent_blend_enable not needed: only one rt supported */
/* XXX alpha_to_coverage / alpha_to_one? */
@ -147,9 +147,9 @@ etna_update_blend(struct etna_context *ctx)
*/
if (pfb->cbufs[0])
desc = util_format_description(pfb->cbufs[0]->format);
bool full_overwrite = !pfb->cbufs[0] || ((blend->fo_allowed &&
bool full_overwrite = !pfb->cbufs[0] || ((blend->rt[0].fo_allowed &&
util_format_colormask_full(desc, colormask)));
blend->PE_COLOR_FORMAT =
blend->rt[0].PE_COLOR_FORMAT =
VIVS_PE_COLOR_FORMAT_COMPONENTS(colormask) |
COND(full_overwrite, VIVS_PE_COLOR_FORMAT_OVERWRITE);

13
src/gallium/drivers/etnaviv/etnaviv_blend.h
View file

@ -32,13 +32,16 @@
struct etna_context;
struct etna_blend_state {
struct pipe_blend_state base;
bool fo_allowed;
struct etna_rt_blend_state {
uint32_t PE_ALPHA_CONFIG;
uint32_t PE_COLOR_FORMAT;
bool fo_allowed : 1;
};
struct etna_blend_state {
struct pipe_blend_state base;
struct etna_rt_blend_state rt[PIPE_MAX_COLOR_BUFS];
uint32_t PE_LOGIC_OP;
uint32_t PE_DITHER[2];
};

4
src/gallium/drivers/etnaviv/etnaviv_emit.c
View file

@ -474,7 +474,7 @@ etna_emit_state(struct etna_context *ctx)
/*01424*/ EMIT_STATE(PE_ALPHA_BLEND_COLOR, ctx->blend_color.PE_ALPHA_BLEND_COLOR);
}
if (unlikely(dirty & (ETNA_DIRTY_BLEND))) {
uint32_t val = etna_blend_state(ctx->blend)->PE_ALPHA_CONFIG;
uint32_t val = etna_blend_state(ctx->blend)->rt[0].PE_ALPHA_CONFIG;
/*01428*/ EMIT_STATE(PE_ALPHA_CONFIG, val);
}
if (unlikely(dirty & (ETNA_DIRTY_BLEND | ETNA_DIRTY_FRAMEBUFFER))) {
@ -483,7 +483,7 @@ etna_emit_state(struct etna_context *ctx)
* as a mask to enable the bits from blend PE_COLOR_FORMAT */
val = ~(VIVS_PE_COLOR_FORMAT_COMPONENTS__MASK |
VIVS_PE_COLOR_FORMAT_OVERWRITE);
val |= etna_blend_state(ctx->blend)->PE_COLOR_FORMAT;
val |= etna_blend_state(ctx->blend)->rt[0].PE_COLOR_FORMAT;
val &= ctx->framebuffer.PE_COLOR_FORMAT;
/*0142C*/ EMIT_STATE(PE_COLOR_FORMAT, val);
}