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i965/fs: Lower 32-wide scratch writes in the generator.
The hardware has messages that can write 32 32bit components at once but the channel enable mask gets messed up. We need to split them into several 16-wide scratch writes for the channel enables to be applied correctly. The SIMD lowering pass cannot be used for this because scratch writes are emitted rather late during register allocation long after SIMD lowering has been done. Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
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a7d319c00b
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1e3c58ffaf
1 changed files with 24 additions and 6 deletions
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@ -1061,14 +1061,32 @@ fs_generator::generate_discard_jump(fs_inst *inst)
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void
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fs_generator::generate_scratch_write(fs_inst *inst, struct brw_reg src)
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{
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assert(inst->exec_size <= 16 || inst->force_writemask_all);
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/* The 32-wide messages only respect the first 16-wide half of the channel
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* enable signals which are replicated identically for the second group of
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* 16 channels, so we cannot use them unless the write is marked
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* force_writemask_all.
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*/
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const unsigned lower_size = inst->force_writemask_all ? inst->exec_size :
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MIN2(16, inst->exec_size);
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const unsigned block_size = 4 * lower_size / REG_SIZE;
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assert(inst->mlen != 0);
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brw_MOV(p,
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brw_uvec_mrf(inst->exec_size, (inst->base_mrf + 1), 0),
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retype(src, BRW_REGISTER_TYPE_UD));
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brw_oword_block_write_scratch(p, brw_message_reg(inst->base_mrf),
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inst->exec_size / 8, inst->offset);
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brw_push_insn_state(p);
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brw_set_default_exec_size(p, cvt(lower_size) - 1);
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brw_set_default_compression(p, lower_size > 8);
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for (unsigned i = 0; i < inst->exec_size / lower_size; i++) {
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brw_set_default_group(p, (inst->force_sechalf ? 8 : 0) + lower_size * i);
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brw_MOV(p, brw_uvec_mrf(lower_size, inst->base_mrf + 1, 0),
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retype(offset(src, block_size * i), BRW_REGISTER_TYPE_UD));
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brw_oword_block_write_scratch(p, brw_message_reg(inst->base_mrf),
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block_size,
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inst->offset + block_size * REG_SIZE * i);
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}
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brw_pop_insn_state(p);
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}
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void
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