From 1e2a5858f436fdc7187e9fb1baa34215ce9c5cc7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Wed, 29 Mar 2023 18:54:07 +0200 Subject: [PATCH] radv: Move radv_nir_lower_intrinsics_early to new file. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Also ran clang-format on the affected code. Signed-off-by: Timur Kristóf Reviewed-by: Samuel Pitoiset Part-of: --- src/amd/vulkan/meson.build | 1 + src/amd/vulkan/nir/radv_nir.h | 2 + .../nir/radv_nir_lower_intrinsics_early.c | 78 +++++++++++++++++++ src/amd/vulkan/radv_shader.c | 51 +----------- 4 files changed, 82 insertions(+), 50 deletions(-) create mode 100644 src/amd/vulkan/nir/radv_nir_lower_intrinsics_early.c diff --git a/src/amd/vulkan/meson.build b/src/amd/vulkan/meson.build index fdc5dd96278..0770d7fbb9b 100644 --- a/src/amd/vulkan/meson.build +++ b/src/amd/vulkan/meson.build @@ -74,6 +74,7 @@ libradv_files = files( 'nir/radv_nir_apply_pipeline_layout.c', 'nir/radv_nir_lower_abi.c', 'nir/radv_nir_lower_fs_intrinsics.c', + 'nir/radv_nir_lower_intrinsics_early.c', 'nir/radv_nir_lower_primitive_shading_rate.c', 'nir/radv_nir_lower_ray_queries.c', 'nir/radv_nir_lower_vs_inputs.c', diff --git a/src/amd/vulkan/nir/radv_nir.h b/src/amd/vulkan/nir/radv_nir.h index 3b4e2478d9e..43da0d661fc 100644 --- a/src/amd/vulkan/nir/radv_nir.h +++ b/src/amd/vulkan/nir/radv_nir.h @@ -62,6 +62,8 @@ bool radv_nir_lower_primitive_shading_rate(nir_shader *nir, enum amd_gfx_level g bool radv_nir_lower_fs_intrinsics(nir_shader *nir, const struct radv_pipeline_stage *fs_stage, const struct radv_pipeline_key *key); +bool radv_nir_lower_intrinsics_early(nir_shader *nir, const struct radv_pipeline_key *key); + #ifdef __cplusplus } #endif diff --git a/src/amd/vulkan/nir/radv_nir_lower_intrinsics_early.c b/src/amd/vulkan/nir/radv_nir_lower_intrinsics_early.c new file mode 100644 index 00000000000..51b9d928976 --- /dev/null +++ b/src/amd/vulkan/nir/radv_nir_lower_intrinsics_early.c @@ -0,0 +1,78 @@ +/* + * Copyright © 2016 Red Hat. + * Copyright © 2016 Bas Nieuwenhuizen + * Copyright © 2023 Valve Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +#include "nir.h" +#include "nir_builder.h" +#include "radv_nir.h" +#include "radv_private.h" + +bool +radv_nir_lower_intrinsics_early(nir_shader *nir, const struct radv_pipeline_key *key) +{ + nir_function_impl *entry = nir_shader_get_entrypoint(nir); + bool progress = false; + nir_builder b; + + nir_builder_init(&b, entry); + + nir_foreach_block (block, entry) { + nir_foreach_instr_safe (instr, block) { + if (instr->type != nir_instr_type_intrinsic) + continue; + + nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr); + b.cursor = nir_before_instr(&intrin->instr); + + nir_ssa_def *def = NULL; + switch (intrin->intrinsic) { + case nir_intrinsic_is_sparse_texels_resident: + def = nir_ieq_imm(&b, intrin->src[0].ssa, 0); + break; + case nir_intrinsic_sparse_residency_code_and: + def = nir_ior(&b, intrin->src[0].ssa, intrin->src[1].ssa); + break; + case nir_intrinsic_load_view_index: + if (key->has_multiview_view_index) + continue; + def = nir_imm_zero(&b, 1, 32); + break; + default: + continue; + } + + nir_ssa_def_rewrite_uses(&intrin->dest.ssa, def); + + nir_instr_remove(instr); + progress = true; + } + } + + if (progress) + nir_metadata_preserve(entry, nir_metadata_block_index | nir_metadata_dominance); + else + nir_metadata_preserve(entry, nir_metadata_all); + + return progress; +} diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c index e62984fb1a3..4c77cf7ed03 100644 --- a/src/amd/vulkan/radv_shader.c +++ b/src/amd/vulkan/radv_shader.c @@ -328,55 +328,6 @@ radv_compiler_debug(void *private_data, enum aco_compiler_debug_level level, con NULL, 0, 0, "radv", message); } -static bool -lower_intrinsics(nir_shader *nir, const struct radv_pipeline_key *key) -{ - nir_function_impl *entry = nir_shader_get_entrypoint(nir); - bool progress = false; - nir_builder b; - - nir_builder_init(&b, entry); - - nir_foreach_block (block, entry) { - nir_foreach_instr_safe (instr, block) { - if (instr->type != nir_instr_type_intrinsic) - continue; - - nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr); - b.cursor = nir_before_instr(&intrin->instr); - - nir_ssa_def *def = NULL; - switch (intrin->intrinsic) { - case nir_intrinsic_is_sparse_texels_resident: - def = nir_ieq_imm(&b, intrin->src[0].ssa, 0); - break; - case nir_intrinsic_sparse_residency_code_and: - def = nir_ior(&b, intrin->src[0].ssa, intrin->src[1].ssa); - break; - case nir_intrinsic_load_view_index: - if (key->has_multiview_view_index) - continue; - def = nir_imm_zero(&b, 1, 32); - break; - default: - continue; - } - - nir_ssa_def_rewrite_uses(&intrin->dest.ssa, def); - - nir_instr_remove(instr); - progress = true; - } - } - - if (progress) - nir_metadata_preserve(entry, nir_metadata_block_index | nir_metadata_dominance); - else - nir_metadata_preserve(entry, nir_metadata_all); - - return progress; -} - static bool is_sincos(const nir_instr *instr, const void *_) { @@ -748,7 +699,7 @@ radv_shader_spirv_to_nir(struct radv_device *device, const struct radv_pipeline_ NIR_PASS(_, nir, nir_lower_explicit_io, nir_var_mem_ubo | nir_var_mem_ssbo, nir_address_format_vec2_index_32bit_offset); - NIR_PASS(_, nir, lower_intrinsics, key); + NIR_PASS(_, nir, radv_nir_lower_intrinsics_early, key); /* Lower deref operations for compute shared memory. */ if (nir->info.stage == MESA_SHADER_COMPUTE ||