From 1e0e116d6d0f974805423fa322eaf07a62be4c88 Mon Sep 17 00:00:00 2001 From: Kenneth Graunke Date: Fri, 23 Sep 2011 23:32:56 -0700 Subject: [PATCH] i965: Fix incorrect maximum PS thread count shift on Ivybridge. At one point, the documentation said that max thread count in 3DSTATE_PS was at bit offset 23, but it's actually 24 on Ivybridge. Not only did this halve our thread count, it caused us to write 1 into a bit 23, which is marked as MBZ (must be zero). Furthermore, it made us write an even number into this field, which is apparently not allowed. Apparently we were just lucky it worked. NOTE: This is a candidate for the 7.11 branch. Signed-off-by: Kenneth Graunke Reviewed-by: Eric Anholt (cherry picked from commit 556e7eea80de778b44a37d51cb757ce32221d1e3) --- src/mesa/drivers/dri/i965/brw_defines.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h index 6d41b1e69d3..1fc845a5fc4 100644 --- a/src/mesa/drivers/dri/i965/brw_defines.h +++ b/src/mesa/drivers/dri/i965/brw_defines.h @@ -1266,7 +1266,7 @@ # define GEN7_PS_FLOATING_POINT_MODE_ALT (1 << 16) /* DW3: scratch space */ /* DW4 */ -# define GEN7_PS_MAX_THREADS_SHIFT 23 +# define GEN7_PS_MAX_THREADS_SHIFT 24 # define GEN7_PS_PUSH_CONSTANT_ENABLE (1 << 11) # define GEN7_PS_ATTRIBUTE_ENABLE (1 << 10) # define GEN7_PS_OMASK_TO_RENDER_TARGET (1 << 9)