mirror of
https://gitlab.freedesktop.org/mesa/mesa.git
synced 2026-05-07 13:38:06 +02:00
freedreno/ir3: fix sam.s2en encoding
Signed-off-by: Rob Clark <robdclark@gmail.com>
This commit is contained in:
parent
45b7a581b4
commit
1dffb089f9
2 changed files with 12 additions and 9 deletions
|
|
@ -446,15 +446,17 @@ static int emit_cat5(struct ir3_instruction *instr, void *ptr,
|
||||||
struct ir3_info *info)
|
struct ir3_info *info)
|
||||||
{
|
{
|
||||||
struct ir3_register *dst = instr->regs[0];
|
struct ir3_register *dst = instr->regs[0];
|
||||||
struct ir3_register *src1 = instr->regs[1];
|
/* To simplify things when there could be zero, one, or two args other
|
||||||
struct ir3_register *src2 = instr->regs[2];
|
* than tex/sampler idx, we use the first src reg in the ir to hold
|
||||||
struct ir3_register *src3 = instr->regs[3];
|
* samp_tex hvec2:
|
||||||
|
*/
|
||||||
|
struct ir3_register *src1 = instr->regs[2];
|
||||||
|
struct ir3_register *src2 = instr->regs[3];
|
||||||
instr_cat5_t *cat5 = ptr;
|
instr_cat5_t *cat5 = ptr;
|
||||||
|
|
||||||
iassert_type(dst, type_size(instr->cat5.type) == 32)
|
iassert_type(dst, type_size(instr->cat5.type) == 32)
|
||||||
|
|
||||||
assume(src1 || !src2);
|
assume(src1 || !src2);
|
||||||
assume(src2 || !src3);
|
|
||||||
|
|
||||||
if (src1) {
|
if (src1) {
|
||||||
cat5->full = ! (src1->flags & IR3_REG_HALF);
|
cat5->full = ! (src1->flags & IR3_REG_HALF);
|
||||||
|
|
@ -462,17 +464,15 @@ static int emit_cat5(struct ir3_instruction *instr, void *ptr,
|
||||||
}
|
}
|
||||||
|
|
||||||
if (instr->flags & IR3_INSTR_S2EN) {
|
if (instr->flags & IR3_INSTR_S2EN) {
|
||||||
|
struct ir3_register *samp_tex = instr->regs[1];
|
||||||
if (src2) {
|
if (src2) {
|
||||||
iassert(!((src1->flags ^ src2->flags) & IR3_REG_HALF));
|
iassert(!((src1->flags ^ src2->flags) & IR3_REG_HALF));
|
||||||
cat5->s2en.src2 = reg(src2, info, instr->repeat, IR3_REG_HALF);
|
cat5->s2en.src2 = reg(src2, info, instr->repeat, IR3_REG_HALF);
|
||||||
}
|
}
|
||||||
if (src3) {
|
iassert(samp_tex->flags & IR3_REG_HALF);
|
||||||
iassert(src3->flags & IR3_REG_HALF);
|
cat5->s2en.src3 = reg(samp_tex, info, instr->repeat, IR3_REG_HALF);
|
||||||
cat5->s2en.src3 = reg(src3, info, instr->repeat, IR3_REG_HALF);
|
|
||||||
}
|
|
||||||
iassert(!(instr->cat5.samp | instr->cat5.tex));
|
iassert(!(instr->cat5.samp | instr->cat5.tex));
|
||||||
} else {
|
} else {
|
||||||
iassert(!src3);
|
|
||||||
if (src2) {
|
if (src2) {
|
||||||
iassert(!((src1->flags ^ src2->flags) & IR3_REG_HALF));
|
iassert(!((src1->flags ^ src2->flags) & IR3_REG_HALF));
|
||||||
cat5->norm.src2 = reg(src2, info, instr->repeat, IR3_REG_HALF);
|
cat5->norm.src2 = reg(src2, info, instr->repeat, IR3_REG_HALF);
|
||||||
|
|
|
||||||
|
|
@ -1339,6 +1339,9 @@ ir3_SAM(struct ir3_block *block, opc_t opc, type_t type,
|
||||||
sam = ir3_instr_create(block, opc);
|
sam = ir3_instr_create(block, opc);
|
||||||
sam->flags |= flags;
|
sam->flags |= flags;
|
||||||
ir3_reg_create(sam, 0, 0)->wrmask = wrmask;
|
ir3_reg_create(sam, 0, 0)->wrmask = wrmask;
|
||||||
|
// temporary step, extra dummy src which will become the
|
||||||
|
// hvec2(samp, tex) argument:
|
||||||
|
ir3_reg_create(sam, 0, 0);
|
||||||
if (src0) {
|
if (src0) {
|
||||||
reg = ir3_reg_create(sam, 0, IR3_REG_SSA);
|
reg = ir3_reg_create(sam, 0, IR3_REG_SSA);
|
||||||
reg->wrmask = (1 << (src0->regs_count - 1)) - 1;
|
reg->wrmask = (1 << (src0->regs_count - 1)) - 1;
|
||||||
|
|
|
||||||
Loading…
Add table
Reference in a new issue