From 1d3542694bd26d6a912e558af6421aef8e62758f Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Mon, 19 Apr 2021 08:44:40 +0200 Subject: [PATCH] radv: fix emitting depth bias when beginning a command buffer If depth bias is enabled but zero values used, they were never emitted to the command buffer because they are equal to the default values. Previously, they were always emitted when the bound DS attachment changed. This should fix some sort of Z fighting with Dota2 on all GPUs. This also fixes a different issue (ie. some occlusion queries failures) on GFX6 because CLEAR_STATE is not used on that chip. Fixes: 8a47422d977 ("radv: do not scale the depth bias for D16_UNORM depth surfaces") Cc: 21.1 mesa-stable Signed-off-by: Samuel Pitoiset Reviewed-by: Bas Nieuwenhuizen Part-of: --- src/amd/vulkan/radv_cmd_buffer.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 67a5aef0d8a..2368efe0cda 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -1262,7 +1262,8 @@ radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer) RADV_CMD_DIRTY_DYNAMIC_CULL_MODE | RADV_CMD_DIRTY_DYNAMIC_FRONT_FACE; if (!cmd_buffer->state.emitted_pipeline) - cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY; + cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY | + RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS; if (!cmd_buffer->state.emitted_pipeline || cmd_buffer->state.emitted_pipeline->graphics.db_depth_control !=