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ir3/ra: assign interval offsets to new defs after shared RA

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Shared RA might insert new defs to be handled by regular RA (e.g.,
shared spills). However, their interval offsets were not initialized
which caused their intervals to sometimes be mistakenly matched with
those containing offset 0. Fix this by calling index_merge_sets after
shared RA and modifying that function to only index new defs in that
case.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Fixes: fa22b0901a ("ir3/ra: Add specialized shared register RA/spilling")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33319>
(cherry picked from commit a0db2f9737)
This commit is contained in:
Job Noorman 2025-03-14 09:00:04 +01:00 • committed by Eric Engestrom
parent ef2a5bee7b
commit 1d1fe5cca3
4 changed files with 21 additions and 4 deletions
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2
.pick_status.json
View file

@ -684,7 +684,7 @@
"description": "ir3/ra: assign interval offsets to new defs after shared RA",
"nominated": true,
"nomination_type": 2,
"resolution": 0,
"resolution": 1,
"main_sha": null,
"because_sha": "fa22b0901af548d5e1433ad4cdbda314182137c5",
"notes": null

17
src/freedreno/ir3/ir3_merge_regs.c
View file

@ -511,14 +511,19 @@ ir3_create_parallel_copies(struct ir3 *ir)
}
static void
index_merge_sets(struct ir3_liveness *live, struct ir3 *ir)
index_merge_sets(struct ir3_liveness *live, struct ir3 *ir, bool update)
{
unsigned offset = 0;
unsigned offset = update ? live->interval_offset : 0;
foreach_block (block, &ir->block_list) {
foreach_instr (instr, &block->instr_list) {
for (unsigned i = 0; i < instr->dsts_count; i++) {
struct ir3_register *dst = instr->dsts[i];
if (update &&
(dst->interval_start != 0 || dst->interval_end != 0)) {
continue;
}
unsigned dst_offset;
struct ir3_merge_set *merge_set = dst->merge_set;
unsigned size = reg_size(dst);
@ -542,6 +547,12 @@ index_merge_sets(struct ir3_liveness *live, struct ir3 *ir)
live->interval_offset = offset;
}
void
ir3_update_merge_sets_index(struct ir3_liveness *live, struct ir3 *ir)
{
index_merge_sets(live, ir, true);
}
#define RESET "\x1b[0m"
#define BLUE "\x1b[0;34m"
#define SYN_SSA(x) BLUE x RESET
@ -617,7 +628,7 @@ ir3_merge_regs(struct ir3_liveness *live, struct ir3 *ir)
}
}
index_merge_sets(live, ir);
index_merge_sets(live, ir, false);
if (ir3_shader_debug & IR3_DBG_RAMSGS)
dump_merge_sets(ir);

1
src/freedreno/ir3/ir3_ra.h
View file

@ -157,6 +157,7 @@ void ir3_merge_regs(struct ir3_liveness *live, struct ir3 *ir);
void ir3_force_merge(struct ir3_register *a, struct ir3_register *b,
int b_offset);
void ir3_update_merge_sets_index(struct ir3_liveness *live, struct ir3 *ir);
void ir3_index_instrs_for_merge_sets(struct ir3 *ir);

5
src/freedreno/ir3/ir3_shared_ra.c
View file

@ -1493,5 +1493,10 @@ ir3_ra_shared(struct ir3_shader_variant *v, struct ir3_liveness **live_ptr)
ralloc_free(live);
*live_ptr = ir3_calc_liveness(live_mem_ctx, v->ir);
(*live_ptr)->interval_offset = interval_offset;
/* We've created instructions that will be handled by regular RA (e.g.,
* shared spills) so make sure they have their interval offsets assigned.
*/
ir3_update_merge_sets_index(*live_ptr, v->ir);
}