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svga: remove svga_get_param and svga_get_paramf
Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32955>
This commit is contained in:
Qiang Yu
Marge Bot
parent
6c17eab006
commit
1d17d5501d
1 changed files with 0 additions and 312 deletions
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@ -132,316 +132,6 @@ get_bool_cap(struct svga_winsys_screen *sws, SVGA3dDevCapIndex cap,
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}
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static float
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svga_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
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{
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struct svga_screen *svgascreen = svga_screen(screen);
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struct svga_winsys_screen *sws = svgascreen->sws;
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switch (param) {
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case PIPE_CAPF_MIN_LINE_WIDTH:
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case PIPE_CAPF_MIN_LINE_WIDTH_AA:
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case PIPE_CAPF_MIN_POINT_SIZE:
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case PIPE_CAPF_MIN_POINT_SIZE_AA:
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return 1;
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case PIPE_CAPF_POINT_SIZE_GRANULARITY:
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case PIPE_CAPF_LINE_WIDTH_GRANULARITY:
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return 0.1;
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case PIPE_CAPF_MAX_LINE_WIDTH:
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return svgascreen->maxLineWidth;
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case PIPE_CAPF_MAX_LINE_WIDTH_AA:
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return svgascreen->maxLineWidthAA;
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case PIPE_CAPF_MAX_POINT_SIZE:
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FALLTHROUGH;
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case PIPE_CAPF_MAX_POINT_SIZE_AA:
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return svgascreen->maxPointSize;
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case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
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return (float) get_uint_cap(sws, SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY, 4);
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case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
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return 15.0;
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case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
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FALLTHROUGH;
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case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
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FALLTHROUGH;
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case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
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return 0.0f;
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}
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debug_printf("Unexpected PIPE_CAPF_ query %u\n", param);
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return 0;
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}
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static int
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svga_get_param(struct pipe_screen *screen, enum pipe_cap param)
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{
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struct svga_screen *svgascreen = svga_screen(screen);
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struct svga_winsys_screen *sws = svgascreen->sws;
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SVGA3dDevCapResult result;
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switch (param) {
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case PIPE_CAP_NPOT_TEXTURES:
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case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
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case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
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return 1;
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case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
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/*
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* "In virtually every OpenGL implementation and hardware,
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* GL_MAX_DUAL_SOURCE_DRAW_BUFFERS is 1"
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* http://www.opengl.org/wiki/Blending
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*/
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return sws->have_vgpu10 ? 1 : 0;
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case PIPE_CAP_ANISOTROPIC_FILTER:
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return 1;
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case PIPE_CAP_MAX_RENDER_TARGETS:
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return svgascreen->max_color_buffers;
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case PIPE_CAP_OCCLUSION_QUERY:
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return 1;
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case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
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return sws->have_vgpu10;
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case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
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return sws->have_vgpu10 ? 16 : 0;
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case PIPE_CAP_TEXTURE_SWIZZLE:
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return 1;
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case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
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return 256;
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case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
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{
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unsigned size = 1 << (SVGA_MAX_TEXTURE_LEVELS - 1);
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if (sws->get_cap(sws, SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH, &result))
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size = MIN2(result.u, size);
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else
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size = 2048;
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if (sws->get_cap(sws, SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT, &result))
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size = MIN2(result.u, size);
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else
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size = 2048;
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return size;
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}
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case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
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if (!sws->get_cap(sws, SVGA3D_DEVCAP_MAX_VOLUME_EXTENT, &result))
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return 8; /* max 128x128x128 */
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return MIN2(util_logbase2(result.u) + 1, SVGA_MAX_TEXTURE_LEVELS);
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case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
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return util_last_bit(screen->get_param(screen, PIPE_CAP_MAX_TEXTURE_2D_SIZE));
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case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
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return sws->have_sm5 ? SVGA3D_SM5_MAX_SURFACE_ARRAYSIZE :
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(sws->have_vgpu10 ? SVGA3D_SM4_MAX_SURFACE_ARRAYSIZE : 0);
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case PIPE_CAP_BLEND_EQUATION_SEPARATE: /* req. for GL 1.5 */
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return 1;
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case PIPE_CAP_FS_COORD_ORIGIN_UPPER_LEFT:
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return 1;
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case PIPE_CAP_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
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return sws->have_vgpu10;
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case PIPE_CAP_FS_COORD_PIXEL_CENTER_INTEGER:
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return !sws->have_vgpu10;
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case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
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return 1; /* The color outputs of vertex shaders are not clamped */
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case PIPE_CAP_VERTEX_COLOR_CLAMPED:
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return sws->have_vgpu10;
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case PIPE_CAP_GLSL_FEATURE_LEVEL:
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case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
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if (sws->have_gl43) {
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return 430;
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} else if (sws->have_sm5) {
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return 410;
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} else if (sws->have_vgpu10) {
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return 330;
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} else {
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return 120;
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}
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case PIPE_CAP_TEXTURE_TRANSFER_MODES:
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return 0;
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case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
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case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
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return 1;
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case PIPE_CAP_DEPTH_CLIP_DISABLE:
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case PIPE_CAP_INDEP_BLEND_ENABLE:
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case PIPE_CAP_CONDITIONAL_RENDER:
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case PIPE_CAP_QUERY_TIMESTAMP:
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case PIPE_CAP_VS_INSTANCEID:
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case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
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case PIPE_CAP_SEAMLESS_CUBE_MAP:
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case PIPE_CAP_FAKE_SW_MSAA:
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return sws->have_vgpu10;
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case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
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return sws->have_vgpu10 ? SVGA3D_DX_MAX_SOTARGETS : 0;
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case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
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return sws->have_vgpu10 ? 4 : 0;
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case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
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return sws->have_sm5 ? SVGA3D_MAX_STREAMOUT_DECLS :
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(sws->have_vgpu10 ? SVGA3D_MAX_DX10_STREAMOUT_DECLS : 0);
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case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
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return sws->have_sm5;
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case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
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return sws->have_sm5;
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case PIPE_CAP_TEXTURE_MULTISAMPLE:
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return svgascreen->ms_samples ? 1 : 0;
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case PIPE_CAP_MAX_TEXEL_BUFFER_ELEMENTS_UINT:
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/* convert bytes to texels for the case of the largest texel
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* size: float[4].
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*/
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return SVGA3D_DX_MAX_RESOURCE_SIZE / (4 * sizeof(float));
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case PIPE_CAP_MIN_TEXEL_OFFSET:
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return sws->have_vgpu10 ? VGPU10_MIN_TEXEL_FETCH_OFFSET : 0;
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case PIPE_CAP_MAX_TEXEL_OFFSET:
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return sws->have_vgpu10 ? VGPU10_MAX_TEXEL_FETCH_OFFSET : 0;
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case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
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case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
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return 0;
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case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
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return sws->have_vgpu10 ? 256 : 0;
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case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
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return sws->have_vgpu10 ? 1024 : 0;
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case PIPE_CAP_PRIMITIVE_RESTART:
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case PIPE_CAP_PRIMITIVE_RESTART_FIXED_INDEX:
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return 1; /* may be a sw fallback, depending on restart index */
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case PIPE_CAP_GENERATE_MIPMAP:
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return sws->have_generate_mipmap_cmd;
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case PIPE_CAP_NATIVE_FENCE_FD:
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return sws->have_fence_fd;
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case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
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return 1;
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case PIPE_CAP_CUBE_MAP_ARRAY:
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case PIPE_CAP_INDEP_BLEND_FUNC:
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case PIPE_CAP_SAMPLE_SHADING:
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case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
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case PIPE_CAP_TEXTURE_QUERY_LOD:
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return sws->have_sm4_1;
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case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
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/* SM4_1 supports only single-channel textures where as SM5 supports
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* all four channel textures */
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return sws->have_sm5 ? 4 :
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(sws->have_sm4_1 ? 1 : 0);
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case PIPE_CAP_DRAW_INDIRECT:
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return sws->have_sm5;
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case PIPE_CAP_MAX_VERTEX_STREAMS:
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return sws->have_sm5 ? 4 : 0;
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case PIPE_CAP_COMPUTE:
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return sws->have_gl43;
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case PIPE_CAP_MAX_VARYINGS:
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/* According to the spec, max varyings does not include the components
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* for position, so remove one count from the max for position.
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*/
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return sws->have_vgpu10 ? VGPU10_MAX_PS_INPUTS-1 : 10;
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case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
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return sws->have_coherent;
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case PIPE_CAP_START_INSTANCE:
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return sws->have_sm5;
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case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
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return sws->have_sm5;
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case PIPE_CAP_SAMPLER_VIEW_TARGET:
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return sws->have_gl43;
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case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
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return sws->have_gl43;
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case PIPE_CAP_CLIP_HALFZ:
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return sws->have_gl43;
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case PIPE_CAP_SHAREABLE_SHADERS:
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return 0;
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case PIPE_CAP_PCI_GROUP:
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case PIPE_CAP_PCI_BUS:
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case PIPE_CAP_PCI_DEVICE:
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case PIPE_CAP_PCI_FUNCTION:
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return 0;
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case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
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return sws->have_gl43 ? 16 : 0;
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case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
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case PIPE_CAP_MAX_COMBINED_SHADER_BUFFERS:
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return sws->have_gl43 ? SVGA_MAX_SHADER_BUFFERS : 0;
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case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTERS:
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case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTER_BUFFERS:
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return sws->have_gl43 ? SVGA_MAX_ATOMIC_BUFFERS : 0;
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case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
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return 64;
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case PIPE_CAP_VERTEX_INPUT_ALIGNMENT:
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return sws->have_vgpu10 ? PIPE_VERTEX_INPUT_ALIGNMENT_ELEMENT : PIPE_VERTEX_INPUT_ALIGNMENT_4BYTE;
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case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
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return 2048;
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case PIPE_CAP_MAX_VIEWPORTS:
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assert((!sws->have_vgpu10 && svgascreen->max_viewports == 1) ||
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(sws->have_vgpu10 &&
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svgascreen->max_viewports == SVGA3D_DX_MAX_VIEWPORTS));
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return svgascreen->max_viewports;
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case PIPE_CAP_ENDIANNESS:
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return PIPE_ENDIAN_LITTLE;
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case PIPE_CAP_VENDOR_ID:
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return 0x15ad; /* VMware Inc. */
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case PIPE_CAP_DEVICE_ID:
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if (sws->device_id) {
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return sws->device_id;
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} else {
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return 0x0405; /* assume SVGA II */
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}
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case PIPE_CAP_ACCELERATED:
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return 0; /* XXX: */
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case PIPE_CAP_VIDEO_MEMORY:
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/* XXX: Query the host ? */
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return 1;
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case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
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return sws->have_vgpu10;
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case PIPE_CAP_DOUBLES:
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return sws->have_sm5;
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case PIPE_CAP_UMA:
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case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
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return 0;
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case PIPE_CAP_TGSI_DIV:
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return 1;
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case PIPE_CAP_MAX_GS_INVOCATIONS:
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return 32;
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case PIPE_CAP_MAX_SHADER_BUFFER_SIZE_UINT:
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return 1 << 27;
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/* Verify this once protocol is finalized. Setting it to minimum value. */
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case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
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return sws->have_sm5 ? 30 : 0;
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case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
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return 1;
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case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
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return 1;
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case PIPE_CAP_TGSI_TEXCOORD:
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return sws->have_vgpu10 ? 1 : 0;
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case PIPE_CAP_IMAGE_STORE_FORMATTED:
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return sws->have_gl43;
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default:
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return u_pipe_screen_get_param_defaults(screen, param);
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}
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}
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static int
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vgpu9_get_shader_param(struct pipe_screen *screen,
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enum pipe_shader_type shader,
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@ -1244,10 +934,8 @@ svga_screen_create(struct svga_winsys_screen *sws)
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screen->get_vendor = svga_get_vendor;
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screen->get_device_vendor = svga_get_vendor; // TODO actual device vendor
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screen->get_screen_fd = svga_screen_get_fd;
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screen->get_param = svga_get_param;
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screen->get_shader_param = svga_get_shader_param;
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screen->get_compiler_options = svga_get_compiler_options;
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screen->get_paramf = svga_get_paramf;
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screen->get_timestamp = NULL;
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screen->is_format_supported = svga_is_format_supported;
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screen->context_create = svga_context_create;
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