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radeonsi: set *outputs_written in scan_io_usage instead of later
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32171>
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commit
1d16d88e1e
1 changed files with 35 additions and 35 deletions
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@ -172,6 +172,7 @@ static void scan_io_usage(const nir_shader *nir, struct si_shader_info *info,
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for (unsigned i = 0; i < num_slots; i++) {
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unsigned loc = driver_location + i;
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unsigned slot_semantic = semantic + i;
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/* Call the translation functions to validate the semantic (call assertions in them). */
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if (nir->info.stage != MESA_SHADER_FRAGMENT &&
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@ -180,14 +181,14 @@ static void scan_io_usage(const nir_shader *nir, struct si_shader_info *info,
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semantic == VARYING_SLOT_TESS_LEVEL_OUTER ||
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(semantic >= VARYING_SLOT_PATCH0 && semantic <= VARYING_SLOT_PATCH31)) {
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ac_shader_io_get_unique_index_patch(semantic);
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ac_shader_io_get_unique_index_patch(semantic + i);
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ac_shader_io_get_unique_index_patch(slot_semantic);
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} else {
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si_shader_io_get_unique_index(semantic);
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si_shader_io_get_unique_index(semantic + i);
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si_shader_io_get_unique_index(slot_semantic);
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}
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}
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info->output_semantic[loc] = semantic + i;
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info->output_semantic[loc] = slot_semantic;
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if (!is_output_load && mask) {
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/* Output stores. */
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@ -225,6 +226,37 @@ static void scan_io_usage(const nir_shader *nir, struct si_shader_info *info,
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info->output_usagemask[loc] |= mask;
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info->num_outputs = MAX2(info->num_outputs, loc + 1);
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if (nir->info.stage == MESA_SHADER_VERTEX ||
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nir->info.stage == MESA_SHADER_TESS_CTRL ||
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nir->info.stage == MESA_SHADER_TESS_EVAL ||
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nir->info.stage == MESA_SHADER_GEOMETRY) {
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if (slot_semantic == VARYING_SLOT_TESS_LEVEL_INNER ||
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slot_semantic == VARYING_SLOT_TESS_LEVEL_OUTER ||
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(slot_semantic >= VARYING_SLOT_PATCH0 &&
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slot_semantic < VARYING_SLOT_TESS_MAX)) {
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info->patch_outputs_written |=
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BITFIELD_BIT(ac_shader_io_get_unique_index_patch(slot_semantic));
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} else if ((slot_semantic <= VARYING_SLOT_VAR31 ||
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slot_semantic >= VARYING_SLOT_VAR0_16BIT) &&
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slot_semantic != VARYING_SLOT_EDGE) {
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/* Ignore outputs that are not passed from VS to PS. */
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if (slot_semantic != VARYING_SLOT_POS &&
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slot_semantic != VARYING_SLOT_PSIZ &&
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slot_semantic != VARYING_SLOT_CLIP_VERTEX &&
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slot_semantic != VARYING_SLOT_LAYER) {
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info->outputs_written_before_ps |=
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BITFIELD64_BIT(si_shader_io_get_unique_index(slot_semantic));
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}
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/* LAYER and VIEWPORT have no effect if they don't feed the rasterizer. */
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if (slot_semantic != VARYING_SLOT_LAYER &&
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slot_semantic != VARYING_SLOT_VIEWPORT) {
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info->outputs_written_before_tes_gs |=
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BITFIELD64_BIT(si_shader_io_get_unique_index(slot_semantic));
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}
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}
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}
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if (nir->info.stage == MESA_SHADER_FRAGMENT &&
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semantic >= FRAG_RESULT_DATA0 && semantic <= FRAG_RESULT_DATA7) {
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unsigned index = semantic - FRAG_RESULT_DATA0;
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@ -638,38 +670,6 @@ void si_nir_scan_shader(struct si_screen *sscreen, const struct nir_shader *nir,
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info->uses_vmem_load_other |= info->uses_indirect_descriptor;
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info->has_divergent_loop = nir_has_divergent_loop((nir_shader*)nir);
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if (nir->info.stage == MESA_SHADER_VERTEX ||
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nir->info.stage == MESA_SHADER_TESS_CTRL ||
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nir->info.stage == MESA_SHADER_TESS_EVAL ||
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nir->info.stage == MESA_SHADER_GEOMETRY) {
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for (unsigned i = 0; i < info->num_outputs; i++) {
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unsigned semantic = info->output_semantic[i];
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if (semantic == VARYING_SLOT_TESS_LEVEL_INNER ||
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semantic == VARYING_SLOT_TESS_LEVEL_OUTER ||
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(semantic >= VARYING_SLOT_PATCH0 && semantic < VARYING_SLOT_TESS_MAX)) {
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info->patch_outputs_written |= 1ull << ac_shader_io_get_unique_index_patch(semantic);
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} else if ((semantic <= VARYING_SLOT_VAR31 || semantic >= VARYING_SLOT_VAR0_16BIT) &&
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semantic != VARYING_SLOT_EDGE) {
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/* Ignore outputs that are not passed from VS to PS. */
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if (semantic != VARYING_SLOT_POS &&
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semantic != VARYING_SLOT_PSIZ &&
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semantic != VARYING_SLOT_CLIP_VERTEX &&
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semantic != VARYING_SLOT_LAYER) {
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info->outputs_written_before_ps |= 1ull
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<< si_shader_io_get_unique_index(semantic);
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}
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/* LAYER and VIEWPORT have no effect if they don't feed the rasterizer. */
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if (semantic != VARYING_SLOT_LAYER &&
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semantic != VARYING_SLOT_VIEWPORT) {
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info->outputs_written_before_tes_gs |=
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BITFIELD64_BIT(si_shader_io_get_unique_index(semantic));
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}
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}
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}
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}
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if (nir->info.stage == MESA_SHADER_VERTEX) {
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info->num_vs_inputs =
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nir->info.stage == MESA_SHADER_VERTEX && !info->base.vs.blit_sgprs_amd ? info->num_inputs : 0;
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