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radv: Handle instruction encodings > 8 bytes when splitting disassembly

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Choosing the wrong instruction length prevents
radv_dump_annotated_shader from matching waves.

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30734>
This commit is contained in:
Konstantin 2024-08-20 10:03:39 +02:00 • committed by Marge Bot
parent db39685e31
commit 1cf507b806
1 changed files with 3 additions and 3 deletions
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6
src/amd/vulkan/radv_debug.c
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@ -231,7 +231,7 @@ radv_dump_descriptors(struct radv_device *device, FILE *f)
struct radv_shader_inst {
char text[160]; /* one disasm line */
unsigned offset; /* instruction offset */
unsigned size; /* instruction size = 4 or 8 */
unsigned size; /* instruction size >= 4 */
};
/* Split a disassembly string into lines and add them to the array pointed
@ -259,8 +259,8 @@ radv_add_split_disasm(const char *disasm, uint64_t start_addr, unsigned *num, st
const char *semicolon = strchr(disasm, ';');
assert(semicolon);
/* More than 16 chars after ";" means the instruction is 8 bytes long. */
inst->size = next - semicolon > 16 ? 8 : 4;
/* 9 = 8 hex digits + a leading space */
inst->size = (next - semicolon) / 9 * 4;
snprintf(inst->text + len, ARRAY_SIZE(inst->text) - len, " [PC=0x%" PRIx64 ", off=%u, size=%u]",
start_addr + inst->offset, inst->offset, inst->size);