fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-01-09 08:20:12 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions 2

freedreno: Document a650-specific CP_REG_WRITE flag

Browse source 
v2: Danylo: clarified previously unknown GRAS_LRZ_CNTL field.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16251>
This commit is contained in:
Connor Abbott 2020-11-13 19:15:54 +01:00 • committed by Marge Bot
parent 5592c366cf
commit 1cd91fdec3
1 changed files with 14 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

15
src/freedreno/registers/adreno/adreno_pm4.xml
View file

@ -1775,9 +1775,22 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords)
register(s) like the others.
</doc>
<value name="UNK_EVENT_WRITE" value="0x4"/>
<doc>
Tracks GRAS_LRZ_CNTL::GREATER, GRAS_LRZ_CNTL::DIR, and
GRAS_UNKNOWN_810A with previous values, and if one of
the following is true:
- GRAS_LRZ_CNTL::GREATER has changed
- GRAS_LRZ_CNTL::DIR has changed, the old value is not
CUR_DIR_GE, and the new value is not CUR_DIR_DISABLED
- GRAS_UNKNOWN_810A has changed
then it does a LRZ_FLUSH with GRAS_LRZ_CNTL::ENABLE
forced to 1.
Only exists in a650_sqe.fw.
</doc>
<value name="TRACK_LRZ" value="0x8"/>
</enum>
<reg32 offset="0" name="0">
<bitfield name="TRACKER" low="0" high="2" type="reg_tracker"/>
<bitfield name="TRACKER" low="0" high="3" type="reg_tracker"/>
</reg32>
</domain>