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anv: remove barrier special handling for RT_BTI_CHANGE

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This has been dead code since commit 4b2b824112.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40388>
This commit is contained in:
Tapani Pälli 2026-03-24 10:12:52 +02:00 • committed by Marge Bot
parent 17a9ee7152
commit 1cce7c79f0
1 changed files with 0 additions and 30 deletions
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30
src/intel/vulkan/genX_cmd_buffer.c
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@ -1990,36 +1990,6 @@ emit_resource_barrier(struct anv_batch *batch,
if (wait_stages == RESOURCE_BARRIER_STAGE_NONE)
wait_stages = RESOURCE_BARRIER_STAGE_TOP;
if (bits & ANV_PIPE_RT_BTI_CHANGE) {
/* We used to deal with RT BTI changes with a PIPE_CONTROL with the
* following flags:
* - RenderTargetCacheFlushEnable
* - StallAtPixelScoreboard
*
* With the new RESOURCE_BARRIER instruction, there is a problem in HW
* if you do something like this:
* Draw BT0=surfaceA
* Type=Immediate Signal=Color Wait=Top Flags=Color
* Draw BT0=surfaceB
*
* The new BTI0 is somehow not updated in the state cache, so the second
* draw color writes are going either to the previous surface or maybe
* /dev/null?
*
* The Windows drivers appear to not experience this because they're
* setting COMMON_SLICE_CHICKEN3:StateCachePerfFixDisabled=true.
*
* We cannot enable this unfortunately because we're still relying
* pretty heavily on the binding table and toggling that bit is big
* performance regression on multiple benchmarks (up to 25%).
*
* So when ANV_PIPE_RT_BTI_CHANGE is set, emit a RT flush + state cache
* invalidation (which seems to correctly invalidate the RCC).
*/
bits |= ANV_PIPE_STATE_CACHE_INVALIDATE_BIT |
ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT;
}
anv_batch_emit(batch, GENX(RESOURCE_BARRIER), barrier) {
barrier.ResourceBarrierBody.BarrierType = barrier_type;
barrier.ResourceBarrierBody.BarrierIDAddress = barrier_addr;