From 1c933b6511de6c48ac49db8a1d04a8519251e877 Mon Sep 17 00:00:00 2001
From: Caio Oliveira <caio.oliveira@intel.com>
Date: Tue, 26 Aug 2025 22:38:33 -0700
Subject: [PATCH] brw: Fix checking sources of wrong instruction in
 opt_address_reg_load

Fixes: 8ac7802ac83 ("brw: move final send lowering up into the IR")
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37019>
---
 src/intel/compiler/brw_opt_address_reg_load.cpp | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/intel/compiler/brw_opt_address_reg_load.cpp b/src/intel/compiler/brw_opt_address_reg_load.cpp
index 70186cbdca9..c9d8d39727b 100644
--- a/src/intel/compiler/brw_opt_address_reg_load.cpp
+++ b/src/intel/compiler/brw_opt_address_reg_load.cpp
@@ -40,7 +40,8 @@ opt_address_reg_load_local(brw_shader &s, bblock_t *block, const brw_def_analysi
       brw_builder ubld = brw_builder(&s).before(inst).uniform();
       brw_reg sources[3];
       for (unsigned i = 0; i < src_inst->sources; i++) {
-         sources[i] = inst->src[i].file == VGRF ? component(src_inst->src[i], 0) : src_inst->src[i];
+         const brw_reg src = src_inst->src[i];
+         sources[i] = src.file == VGRF ? component(src, 0) : src;
       }
       ubld.emit(src_inst->opcode, inst->dst, sources, src_inst->sources);