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freedreno: use imm-helpers
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23855>
This commit is contained in:
Erik Faye-Lund
Marge Bot
parent
45e7e16222
commit
1c524136c0
7 changed files with 34 additions and 35 deletions
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@ -222,7 +222,7 @@ ir3_nir_lower_ssbo_size_instr(nir_builder *b, nir_instr *instr, void *data)
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{
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uint8_t ssbo_size_to_bytes_shift = *(uint8_t *) data;
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nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
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return nir_ishl(b, &intr->dest.ssa, nir_imm_int(b, ssbo_size_to_bytes_shift));
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return nir_ishl_imm(b, &intr->dest.ssa, ssbo_size_to_bytes_shift);
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}
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static bool
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@ -427,7 +427,7 @@ lower_subgroup_id(nir_builder *b, nir_instr *instr, void *unused)
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if (intr->intrinsic == nir_intrinsic_load_subgroup_invocation) {
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return nir_iand(
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b, nir_load_local_invocation_index(b),
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nir_isub(b, nir_load_subgroup_size(b), nir_imm_int(b, 1)));
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nir_iadd_imm(b, nir_load_subgroup_size(b), -1));
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} else if (intr->intrinsic == nir_intrinsic_load_subgroup_id) {
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return nir_ishr(b, nir_load_local_invocation_index(b),
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nir_load_subgroup_id_shift_ir3(b));
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@ -307,8 +307,8 @@ lower_ubo_load_to_uniform(nir_intrinsic_instr *instr, nir_builder *b,
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uniform_offset = new_offset;
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} else {
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uniform_offset = shift > 0
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? nir_ishl(b, ubo_offset, nir_imm_int(b, shift))
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: nir_ushr(b, ubo_offset, nir_imm_int(b, -shift));
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? nir_ishl_imm(b, ubo_offset, shift)
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: nir_ushr_imm(b, ubo_offset, -shift);
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}
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assert(!(const_offset & 0x3));
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@ -98,7 +98,7 @@ lower_64b_intrinsics(nir_builder *b, nir_instr *instr, void *unused)
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nir_intrinsic_set_write_mask(store, 0x3);
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nir_builder_instr_insert(b, &store->instr);
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off = nir_iadd(b, off, nir_imm_intN_t(b, 8, off->bit_size));
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off = nir_iadd_imm(b, off, 8);
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}
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return NIR_LOWER_INSTR_PROGRESS_REPLACE;
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@ -114,9 +114,8 @@ lower_64b_intrinsics(nir_builder *b, nir_instr *instr, void *unused)
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if (intr->intrinsic == nir_intrinsic_load_kernel_input) {
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assert(num_comp == 1);
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nir_ssa_def *offset = nir_iadd(b,
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nir_ssa_for_src(b, intr->src[0], 1),
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nir_imm_int(b, 4));
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nir_ssa_def *offset = nir_iadd_imm(b,
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nir_ssa_for_src(b, intr->src[0], 1), 4);
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nir_ssa_def *upper = nir_load_kernel_input(b, 1, 32, offset);
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@ -150,7 +149,7 @@ lower_64b_intrinsics(nir_builder *b, nir_instr *instr, void *unused)
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components[i] = nir_pack_64_2x32(b, &load->dest.ssa);
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off = nir_iadd(b, off, nir_imm_intN_t(b, 8, off->bit_size));
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off = nir_iadd_imm(b, off, 8);
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}
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} else {
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/* The remaining (non load/store) intrinsics just get zero-
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@ -97,9 +97,9 @@ check_and_propagate_bit_shift32(nir_builder *b, nir_alu_instr *alu_instr,
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/* Add or substract shift depending on the final direction (SHR vs. SHL). */
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if (shift * direction < 0)
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shift_ssa = nir_isub(b, shift_ssa, nir_imm_int(b, abs(shift)));
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shift_ssa = nir_iadd_imm(b, shift_ssa, -abs(shift));
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else
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shift_ssa = nir_iadd(b, shift_ssa, nir_imm_int(b, abs(shift)));
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shift_ssa = nir_iadd_imm(b, shift_ssa, abs(shift));
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return shift_ssa;
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}
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@ -161,8 +161,8 @@ scalarize_load(nir_intrinsic_instr *intrinsic, nir_builder *b)
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for (unsigned i = 0; i < intrinsic->dest.ssa.num_components; i++) {
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results[i] =
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nir_load_ssbo_ir3(b, 1, intrinsic->dest.ssa.bit_size, descriptor,
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nir_iadd(b, offset, nir_imm_int(b, i * comp_size)),
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nir_iadd(b, new_offset, nir_imm_int(b, i)),
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nir_iadd_imm(b, offset, i * comp_size),
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nir_iadd_imm(b, new_offset, i),
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.access = nir_intrinsic_access(intrinsic),
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.align_mul = nir_intrinsic_align_mul(intrinsic),
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.align_offset = nir_intrinsic_align_offset(intrinsic));
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@ -241,7 +241,7 @@ lower_offset_for_ssbo(nir_intrinsic_instr *intrinsic, nir_builder *b,
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if (new_offset)
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offset = new_offset;
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else
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offset = nir_ushr(b, offset, nir_imm_int(b, shift));
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offset = nir_ushr_imm(b, offset, shift);
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/* Insert the new intrinsic right before the old one. */
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nir_builder_instr_insert(b, &new_intrinsic->instr);
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@ -51,8 +51,7 @@ struct state {
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static nir_ssa_def *
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bitfield_extract(nir_builder *b, nir_ssa_def *v, uint32_t start, uint32_t mask)
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{
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return nir_iand(b, nir_ushr(b, v, nir_imm_int(b, start)),
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nir_imm_int(b, mask));
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return nir_iand_imm(b, nir_ushr_imm(b, v, start), mask);
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}
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static nir_ssa_def *
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@ -146,8 +145,8 @@ build_local_offset(nir_builder *b, struct state *state, nir_ssa_def *vertex,
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case MESA_SHADER_TESS_CTRL:
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case MESA_SHADER_GEOMETRY:
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vertex_stride = nir_load_vs_vertex_stride_ir3(b);
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attr_offset = nir_iadd(b, nir_load_primitive_location_ir3(b, index),
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nir_imm_int(b, comp * 4));
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attr_offset = nir_iadd_imm(b, nir_load_primitive_location_ir3(b, index),
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comp * 4);
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break;
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default:
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unreachable("bad shader stage");
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@ -157,7 +156,7 @@ build_local_offset(nir_builder *b, struct state *state, nir_ssa_def *vertex,
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return nir_iadd(
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b, nir_iadd(b, primitive_offset, vertex_offset),
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nir_iadd(b, attr_offset, nir_ishl(b, offset, nir_imm_int(b, 4))));
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nir_iadd(b, attr_offset, nir_ishl_imm(b, offset, 4)));
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}
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static nir_intrinsic_instr *
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@ -417,7 +416,7 @@ build_per_vertex_offset(nir_builder *b, struct state *state,
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/* Offset is in vec4's, but we need it in unit of components for the
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* load/store_global_ir3 offset.
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*/
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offset = nir_ishl(b, offset, nir_imm_int(b, 2));
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offset = nir_ishl_imm(b, offset, 2);
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}
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nir_ssa_def *vertex_offset;
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@ -428,8 +427,8 @@ build_per_vertex_offset(nir_builder *b, struct state *state,
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attr_offset = nir_imm_int(b, state->map.loc[index] + comp);
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break;
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case MESA_SHADER_TESS_EVAL:
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attr_offset = nir_iadd(b, nir_load_primitive_location_ir3(b, index),
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nir_imm_int(b, comp));
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attr_offset = nir_iadd_imm(b, nir_load_primitive_location_ir3(b, index),
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comp);
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break;
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default:
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unreachable("bad shader state");
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@ -437,12 +436,12 @@ build_per_vertex_offset(nir_builder *b, struct state *state,
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attr_offset = nir_iadd(b, attr_offset,
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nir_imul24(b, offset, build_tcs_out_vertices(b)));
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vertex_offset = nir_ishl(b, vertex, nir_imm_int(b, 2));
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vertex_offset = nir_ishl_imm(b, vertex, 2);
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} else {
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assert(location >= VARYING_SLOT_PATCH0 &&
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location <= VARYING_SLOT_TESS_MAX);
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unsigned index = location - VARYING_SLOT_PATCH0;
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attr_offset = nir_iadd(b, nir_imm_int(b, index * 4 + comp), offset);
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attr_offset = nir_iadd_imm(b, offset, index * 4 + comp);
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vertex_offset = nir_imm_int(b, 0);
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}
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@ -506,7 +505,7 @@ build_tessfactor_base(nir_builder *b, gl_varying_slot slot, uint32_t comp,
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unreachable("bad");
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}
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return nir_iadd(b, patch_offset, nir_imm_int(b, offset + comp));
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return nir_iadd_imm(b, patch_offset, offset + comp);
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}
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static void
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@ -886,8 +885,8 @@ lower_gs_block(nir_block *block, nir_builder *b, struct state *state)
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unsigned stream = nir_intrinsic_stream_id(intr);
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/* vertex_flags_out |= stream */
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nir_store_var(b, state->vertex_flags_out,
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nir_ior(b, nir_load_var(b, state->vertex_flags_out),
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nir_imm_int(b, stream)),
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nir_ior_imm(b, nir_load_var(b, state->vertex_flags_out),
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stream),
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0x1 /* .x */);
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copy_vars(b, &state->emit_outputs, &state->old_outputs);
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@ -895,15 +894,17 @@ lower_gs_block(nir_block *block, nir_builder *b, struct state *state)
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nir_instr_remove(&intr->instr);
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nir_store_var(b, state->emitted_vertex_var,
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nir_iadd(b, nir_load_var(b, state->emitted_vertex_var),
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nir_imm_int(b, 1)),
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nir_iadd_imm(b,
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nir_load_var(b,
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state->emitted_vertex_var),
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1),
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0x1);
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nir_pop_if(b, NULL);
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/* Increment the vertex count by 1 */
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nir_store_var(b, state->vertex_count_var,
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nir_iadd(b, count, nir_imm_int(b, 1)), 0x1); /* .x */
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nir_iadd_imm(b, count, 1), 0x1); /* .x */
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nir_store_var(b, state->vertex_flags_out, nir_imm_int(b, 0), 0x1);
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break;
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@ -156,7 +156,7 @@ lower_load_push_constant(struct tu_device *dev,
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nir_ssa_def *load =
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nir_load_uniform(b, instr->num_components,
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instr->dest.ssa.bit_size,
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nir_ushr(b, instr->src[0].ssa, nir_imm_int(b, 2)),
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nir_ushr_imm(b, instr->src[0].ssa, 2),
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.base = base);
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nir_ssa_def_rewrite_uses(&instr->dest.ssa, load);
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@ -283,7 +283,7 @@ lower_ssbo_ubo_intrinsic(struct tu_device *dev,
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intrin->intrinsic == nir_intrinsic_load_ssbo &&
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(nir_intrinsic_access(intrin) & ACCESS_CAN_REORDER) &&
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intrin->dest.ssa.bit_size > 16) {
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descriptor_idx = nir_iadd(b, descriptor_idx, nir_imm_int(b, 1));
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descriptor_idx = nir_iadd_imm(b, descriptor_idx, 1);
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}
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nir_ssa_def *results[MAX_SETS + 1] = { NULL };
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@ -374,8 +374,7 @@ build_bindless(struct tu_device *dev, nir_builder *b,
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return nir_imm_int(b, idx);
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nir_ssa_def *arr_index = nir_ssa_for_src(b, deref->arr.index, 1);
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return nir_iadd(b, nir_imm_int(b, idx),
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nir_imul_imm(b, arr_index, 2));
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return nir_iadd_imm(b, nir_imul_imm(b, arr_index, 2), idx);
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}
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shader->active_desc_sets |= 1u << set;
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@ -62,7 +62,7 @@ lower_intrinsic(nir_builder *b, nir_intrinsic_instr *intr)
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unsigned set = ir3_shader_descriptor_set(b->shader->info.stage);
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nir_ssa_def *src = nir_ssa_for_src(b, intr->src[buffer_src], 1);
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src = nir_iadd(b, src, nir_imm_int(b, desc_offset));
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src = nir_iadd_imm(b, src, desc_offset);
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/* An out-of-bounds index into an SSBO/image array can cause a GPU fault
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* on access to the descriptor (I don't see any hw mechanism to bound the
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* access). We could just allow the resulting iova fault (it is a read
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