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synced 2026-05-05 05:18:08 +02:00
r300: remove unneeded 64bit and atomic lowering passes
Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com> Reviewed-by: Emma Anholt <emma@anholt.net> Reviewed-by: Filip Gawin <filip.gawin@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23437>
This commit is contained in:
Pavel Ondračka
Marge Bot
parent
6b3be0cc2a
commit
1c045c54b7
1 changed files with 0 additions and 296 deletions
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@ -235,20 +235,6 @@ ntr_src_as_uint(struct ntr_compile *c, nir_src src)
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return val;
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}
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static unsigned
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ntr_64bit_write_mask(unsigned write_mask)
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{
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return ((write_mask & 1) ? 0x3 : 0) | ((write_mask & 2) ? 0xc : 0);
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}
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static struct ureg_src
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ntr_64bit_1f(struct ntr_compile *c)
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{
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return ureg_imm4u(c->ureg,
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0x00000000, 0x3ff00000,
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0x00000000, 0x3ff00000);
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}
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/* Per-channel masks of def/use within the block, and the per-channel
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* livein/liveout for the block as a whole.
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*/
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@ -1537,8 +1523,6 @@ ntr_emit_load_ubo(struct ntr_compile *c, nir_intrinsic_instr *instr)
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}
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int start_component = nir_intrinsic_component(instr);
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if (bit_size == 64)
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start_component *= 2;
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src = ntr_shift_by_frac(src, start_component,
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instr->num_components * bit_size / 32);
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@ -2461,7 +2445,6 @@ ntr_optimize_nir(struct nir_shader *s, struct pipe_screen *screen,
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progress = false;
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NIR_PASS_V(s, nir_lower_vars_to_ssa);
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NIR_PASS_V(s, nir_split_64bit_vec3_and_vec4);
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NIR_PASS(progress, s, nir_copy_prop);
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NIR_PASS(progress, s, nir_opt_algebraic);
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@ -2516,212 +2499,6 @@ ntr_optimize_nir(struct nir_shader *s, struct pipe_screen *screen,
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NIR_PASS_V(s, nir_lower_var_copies);
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}
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/* Scalarizes all 64-bit ALU ops. Note that we only actually need to
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* scalarize vec3/vec4s, should probably fix that.
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*/
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static bool
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scalarize_64bit(const nir_instr *instr, const void *data)
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{
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const nir_alu_instr *alu = nir_instr_as_alu(instr);
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return (alu->def.bit_size == 64 ||
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nir_src_bit_size(alu->src[0].src) == 64);
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}
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static bool
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nir_to_rc_lower_64bit_intrinsic(nir_builder *b, nir_intrinsic_instr *instr)
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{
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b->cursor = nir_after_instr(&instr->instr);
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switch (instr->intrinsic) {
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case nir_intrinsic_load_ubo:
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case nir_intrinsic_load_ubo_vec4:
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case nir_intrinsic_load_ssbo:
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case nir_intrinsic_load_input:
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case nir_intrinsic_load_interpolated_input:
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case nir_intrinsic_load_per_vertex_input:
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case nir_intrinsic_store_output:
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case nir_intrinsic_store_per_vertex_output:
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case nir_intrinsic_store_ssbo:
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break;
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default:
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return false;
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}
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if (instr->num_components <= 2)
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return false;
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bool has_dest = nir_intrinsic_infos[instr->intrinsic].has_dest;
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if (has_dest) {
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if (instr->def.bit_size != 64)
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return false;
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} else {
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if (nir_src_bit_size(instr->src[0]) != 64)
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return false;
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}
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nir_intrinsic_instr *first =
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nir_instr_as_intrinsic(nir_instr_clone(b->shader, &instr->instr));
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nir_intrinsic_instr *second =
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nir_instr_as_intrinsic(nir_instr_clone(b->shader, &instr->instr));
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switch (instr->intrinsic) {
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case nir_intrinsic_load_ubo:
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case nir_intrinsic_load_ubo_vec4:
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case nir_intrinsic_load_ssbo:
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case nir_intrinsic_store_ssbo:
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break;
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default: {
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nir_io_semantics semantics = nir_intrinsic_io_semantics(second);
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semantics.location++;
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semantics.num_slots--;
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nir_intrinsic_set_io_semantics(second, semantics);
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nir_intrinsic_set_base(second, nir_intrinsic_base(second) + 1);
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break;
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}
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}
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first->num_components = 2;
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second->num_components -= 2;
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if (has_dest) {
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first->def.num_components = 2;
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second->def.num_components -= 2;
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}
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nir_builder_instr_insert(b, &first->instr);
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nir_builder_instr_insert(b, &second->instr);
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if (has_dest) {
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/* Merge the two loads' results back into a vector. */
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nir_scalar channels[4] = {
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nir_get_scalar(&first->def, 0),
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nir_get_scalar(&first->def, 1),
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nir_get_scalar(&second->def, 0),
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nir_get_scalar(&second->def, second->num_components > 1 ? 1 : 0),
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};
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nir_def *new = nir_vec_scalars(b, channels, instr->num_components);
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nir_def_rewrite_uses(&instr->def, new);
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} else {
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/* Split the src value across the two stores. */
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b->cursor = nir_before_instr(&instr->instr);
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nir_def *src0 = instr->src[0].ssa;
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nir_scalar channels[4] = { 0 };
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for (int i = 0; i < instr->num_components; i++)
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channels[i] = nir_get_scalar(src0, i);
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nir_intrinsic_set_write_mask(first, nir_intrinsic_write_mask(instr) & 3);
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nir_intrinsic_set_write_mask(second, nir_intrinsic_write_mask(instr) >> 2);
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nir_src_rewrite(&first->src[0], nir_vec_scalars(b, channels, 2));
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nir_src_rewrite(&second->src[0],
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nir_vec_scalars(b, &channels[2], second->num_components));
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}
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int offset_src = -1;
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uint32_t offset_amount = 16;
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switch (instr->intrinsic) {
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case nir_intrinsic_load_ssbo:
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case nir_intrinsic_load_ubo:
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offset_src = 1;
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break;
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case nir_intrinsic_load_ubo_vec4:
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offset_src = 1;
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offset_amount = 1;
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break;
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case nir_intrinsic_store_ssbo:
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offset_src = 2;
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break;
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default:
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break;
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}
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if (offset_src != -1) {
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b->cursor = nir_before_instr(&second->instr);
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nir_def *second_offset =
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nir_iadd_imm(b, second->src[offset_src].ssa, offset_amount);
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nir_src_rewrite(&second->src[offset_src], second_offset);
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}
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/* DCE stores we generated with no writemask (nothing else does this
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* currently).
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*/
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if (!has_dest) {
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if (nir_intrinsic_write_mask(first) == 0)
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nir_instr_remove(&first->instr);
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if (nir_intrinsic_write_mask(second) == 0)
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nir_instr_remove(&second->instr);
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}
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nir_instr_remove(&instr->instr);
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return true;
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}
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static bool
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nir_to_rc_lower_64bit_load_const(nir_builder *b, nir_load_const_instr *instr)
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{
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int num_components = instr->def.num_components;
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if (instr->def.bit_size != 64 || num_components <= 2)
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return false;
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b->cursor = nir_before_instr(&instr->instr);
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nir_load_const_instr *first =
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nir_load_const_instr_create(b->shader, 2, 64);
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nir_load_const_instr *second =
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nir_load_const_instr_create(b->shader, num_components - 2, 64);
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first->value[0] = instr->value[0];
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first->value[1] = instr->value[1];
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second->value[0] = instr->value[2];
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if (num_components == 4)
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second->value[1] = instr->value[3];
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nir_builder_instr_insert(b, &first->instr);
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nir_builder_instr_insert(b, &second->instr);
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nir_def *channels[4] = {
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nir_channel(b, &first->def, 0),
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nir_channel(b, &first->def, 1),
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nir_channel(b, &second->def, 0),
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num_components == 4 ? nir_channel(b, &second->def, 1) : NULL,
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};
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nir_def *new = nir_vec(b, channels, num_components);
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nir_def_rewrite_uses(&instr->def, new);
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nir_instr_remove(&instr->instr);
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return true;
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}
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static bool
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nir_to_rc_lower_64bit_to_vec2_instr(nir_builder *b, nir_instr *instr,
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void *data)
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{
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switch (instr->type) {
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case nir_instr_type_load_const:
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return nir_to_rc_lower_64bit_load_const(b, nir_instr_as_load_const(instr));
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case nir_instr_type_intrinsic:
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return nir_to_rc_lower_64bit_intrinsic(b, nir_instr_as_intrinsic(instr));
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default:
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return false;
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}
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}
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static bool
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nir_to_rc_lower_64bit_to_vec2(nir_shader *s)
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{
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return nir_shader_instructions_pass(s,
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nir_to_rc_lower_64bit_to_vec2_instr,
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nir_metadata_block_index |
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nir_metadata_dominance,
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NULL);
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}
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struct ntr_lower_tex_state {
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nir_scalar channels[8];
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unsigned i;
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@ -2868,32 +2645,6 @@ ntr_fix_nir_options(struct pipe_screen *screen, struct nir_shader *s,
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}
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}
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static bool
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ntr_lower_atomic_pre_dec_filter(const nir_instr *instr, const void *_data)
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{
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return (instr->type == nir_instr_type_intrinsic &&
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nir_instr_as_intrinsic(instr)->intrinsic == nir_intrinsic_atomic_counter_pre_dec);
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}
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static nir_def *
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ntr_lower_atomic_pre_dec_lower(nir_builder *b, nir_instr *instr, void *_data)
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{
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nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
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nir_def *old_result = &intr->def;
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intr->intrinsic = nir_intrinsic_atomic_counter_post_dec;
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return nir_iadd_imm(b, old_result, -1);
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}
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static bool
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ntr_lower_atomic_pre_dec(nir_shader *s)
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{
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return nir_shader_lower_instructions(s,
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ntr_lower_atomic_pre_dec_filter,
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ntr_lower_atomic_pre_dec_lower, NULL);
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}
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/* Lowers texture projectors if we can't do them as TGSI_OPCODE_TXP. */
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static void
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nir_to_rc_lower_txp(nir_shader *s)
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@ -2933,36 +2684,6 @@ nir_to_rc_lower_txp(nir_shader *s)
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NIR_PASS_V(s, nir_lower_tex, &lower_tex_options);
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}
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static bool
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nir_lower_primid_sysval_to_input_filter(const nir_instr *instr, const void *_data)
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{
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return (instr->type == nir_instr_type_intrinsic &&
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nir_instr_as_intrinsic(instr)->intrinsic == nir_intrinsic_load_primitive_id);
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}
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static nir_def *
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nir_lower_primid_sysval_to_input_lower(nir_builder *b, nir_instr *instr, void *data)
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{
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nir_variable *var = nir_get_variable_with_location(b->shader, nir_var_shader_in,
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VARYING_SLOT_PRIMITIVE_ID, glsl_uint_type());
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nir_io_semantics semantics = {
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.location = var->data.location,
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.num_slots = 1
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};
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return nir_load_input(b, 1, 32, nir_imm_int(b, 0),
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.base = var->data.driver_location,
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.io_semantics = semantics);
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}
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static bool
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nir_lower_primid_sysval_to_input(nir_shader *s)
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{
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return nir_shader_lower_instructions(s,
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nir_lower_primid_sysval_to_input_filter,
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nir_lower_primid_sysval_to_input_lower, NULL);
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}
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const void *
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nir_to_rc(struct nir_shader *s,
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struct pipe_screen *screen)
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@ -3009,29 +2730,12 @@ const void *nir_to_rc_options(struct nir_shader *s,
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nir_to_rc_lower_txp(s);
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NIR_PASS_V(s, nir_to_rc_lower_tex);
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/* While TGSI can represent PRIMID as either an input or a system value,
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* glsl-to-tgsi had the GS (not TCS or TES) primid as an input, and drivers
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* depend on that.
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*/
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if (s->info.stage == MESA_SHADER_GEOMETRY)
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NIR_PASS_V(s, nir_lower_primid_sysval_to_input);
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if (s->info.num_abos)
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NIR_PASS_V(s, ntr_lower_atomic_pre_dec);
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if (!original_options->lower_uniforms_to_ubo) {
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NIR_PASS_V(s, nir_lower_uniforms_to_ubo,
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screen->get_param(screen, PIPE_CAP_PACKED_UNIFORMS),
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true);
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}
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/* Do lowering so we can directly translate f64/i64 NIR ALU ops to TGSI --
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* TGSI stores up to a vec2 in each slot, so to avoid a whole bunch of op
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* duplication logic we just make it so that we only see vec2s.
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*/
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NIR_PASS_V(s, nir_lower_alu_to_scalar, scalarize_64bit, NULL);
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NIR_PASS_V(s, nir_to_rc_lower_64bit_to_vec2);
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if (!screen->get_param(screen, PIPE_CAP_LOAD_CONSTBUF))
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NIR_PASS_V(s, nir_lower_ubo_vec4);
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