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nak: Implement quad ops
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26264>
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parent
cca40086c6
commit
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1 changed files with 31 additions and 8 deletions
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@ -1848,7 +1848,8 @@ impl<'a> ShaderFromNir<'a> {
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});
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});
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}
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}
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}
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}
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nir_intrinsic_read_invocation
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nir_intrinsic_quad_broadcast
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| nir_intrinsic_read_invocation
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| nir_intrinsic_shuffle
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| nir_intrinsic_shuffle
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| nir_intrinsic_shuffle_down
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| nir_intrinsic_shuffle_down
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| nir_intrinsic_shuffle_up
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| nir_intrinsic_shuffle_up
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@ -1868,22 +1869,44 @@ impl<'a> ShaderFromNir<'a> {
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in_bounds: Dst::None,
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in_bounds: Dst::None,
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src: data,
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src: data,
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lane: idx,
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lane: idx,
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c: if intrin.intrinsic == nir_intrinsic_shuffle_up {
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c: match intrin.intrinsic {
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0.into()
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nir_intrinsic_quad_broadcast => 0x1c_03.into(),
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} else {
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nir_intrinsic_shuffle_up => 0.into(),
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0x1f.into()
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_ => 0x1f.into(),
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},
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},
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op: match intrin.intrinsic {
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op: match intrin.intrinsic {
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nir_intrinsic_read_invocation
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| nir_intrinsic_shuffle => ShflOp::Idx,
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nir_intrinsic_shuffle_down => ShflOp::Down,
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nir_intrinsic_shuffle_down => ShflOp::Down,
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nir_intrinsic_shuffle_up => ShflOp::Up,
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nir_intrinsic_shuffle_up => ShflOp::Up,
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nir_intrinsic_shuffle_xor => ShflOp::Bfly,
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nir_intrinsic_shuffle_xor => ShflOp::Bfly,
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op => panic!("Unknown shuffle intrinsic {}", op),
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_ => ShflOp::Idx,
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},
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},
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});
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});
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self.set_dst(&intrin.def, dst);
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self.set_dst(&intrin.def, dst);
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}
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}
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nir_intrinsic_quad_swap_horizontal
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| nir_intrinsic_quad_swap_vertical
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| nir_intrinsic_quad_swap_diagonal => {
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assert!(srcs[0].bit_size() == 32);
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assert!(srcs[0].num_components() == 1);
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let data = self.get_src(&srcs[0]);
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assert!(intrin.def.bit_size() == 32);
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let dst = b.alloc_ssa(RegFile::GPR, 1);
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b.push_op(OpShfl {
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dst: dst.into(),
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in_bounds: Dst::None,
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src: data,
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lane: match intrin.intrinsic {
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nir_intrinsic_quad_swap_horizontal => 1_u32.into(),
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nir_intrinsic_quad_swap_vertical => 2_u32.into(),
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nir_intrinsic_quad_swap_diagonal => 3_u32.into(),
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op => panic!("Unknown quad intrinsic {}", op),
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},
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c: 0x1c_03.into(),
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op: ShflOp::Bfly,
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});
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self.set_dst(&intrin.def, dst);
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}
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nir_intrinsic_shared_atomic => {
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nir_intrinsic_shared_atomic => {
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let bit_size = intrin.def.bit_size();
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let bit_size = intrin.def.bit_size();
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let (addr, offset) = self.get_io_addr_offset(&srcs[0], 24);
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let (addr, offset) = self.get_io_addr_offset(&srcs[0], 24);
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