mirror of
https://gitlab.freedesktop.org/mesa/mesa.git
synced 2026-05-08 04:48:08 +02:00
nak/sm70: Re-organize the code a bit
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30141>
This commit is contained in:
Faith Ekstrand
Marge Bot
parent
20e1160f3f
commit
1b9b6a9529
1 changed files with 187 additions and 180 deletions
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@ -97,10 +97,193 @@ impl ShaderModel for ShaderModel70 {
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}
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}
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/// A per-op trait that implements Volta+ opcode semantics
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trait SM70Op {
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fn encode(&self, e: &mut SM70Encoder<'_>);
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}
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struct SM70Encoder<'a> {
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sm: &'a ShaderModel70,
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ip: usize,
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labels: &'a HashMap<Label, usize>,
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inst: [u32; 4],
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}
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impl BitViewable for SM70Encoder<'_> {
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fn bits(&self) -> usize {
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BitView::new(&self.inst).bits()
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}
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fn get_bit_range_u64(&self, range: Range<usize>) -> u64 {
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BitView::new(&self.inst).get_bit_range_u64(range)
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}
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}
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impl BitMutViewable for SM70Encoder<'_> {
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fn set_bit_range_u64(&mut self, range: Range<usize>, val: u64) {
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BitMutView::new(&mut self.inst).set_bit_range_u64(range, val);
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}
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}
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impl SetFieldU64 for SM70Encoder<'_> {
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fn set_field_u64(&mut self, range: Range<usize>, val: u64) {
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BitMutView::new(&mut self.inst).set_field_u64(range, val);
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}
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}
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impl SM70Encoder<'_> {
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fn set_opcode(&mut self, opcode: u16) {
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self.set_field(0..12, opcode);
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}
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fn set_reg(&mut self, range: Range<usize>, reg: RegRef) {
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assert!(range.len() == 8);
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assert!(reg.file() == RegFile::GPR);
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self.set_field(range, reg.base_idx());
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}
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fn set_ureg(&mut self, range: Range<usize>, reg: RegRef) {
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assert!(self.sm.sm >= 75);
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assert!(range.len() == 8);
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assert!(reg.file() == RegFile::UGPR);
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assert!(reg.base_idx() <= 63);
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self.set_field(range, reg.base_idx());
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}
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fn set_pred_reg(&mut self, range: Range<usize>, reg: RegRef) {
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assert!(range.len() == 3);
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assert!(reg.base_idx() <= 7);
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assert!(reg.comps() == 1);
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self.set_field(range, reg.base_idx());
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}
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fn set_reg_src(&mut self, range: Range<usize>, src: Src) {
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assert!(src.src_mod.is_none());
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match src.src_ref {
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SrcRef::Zero => self.set_reg(range, RegRef::zero(RegFile::GPR, 1)),
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SrcRef::Reg(reg) => self.set_reg(range, reg),
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_ => panic!("Not a register"),
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}
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}
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fn set_pred_dst(&mut self, range: Range<usize>, dst: Dst) {
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match dst {
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Dst::None => {
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self.set_pred_reg(range, RegRef::zero(RegFile::Pred, 1));
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}
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Dst::Reg(reg) => self.set_pred_reg(range, reg),
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_ => panic!("Not a register"),
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}
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}
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fn set_pred_src_file(
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&mut self,
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range: Range<usize>,
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not_bit: usize,
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src: Src,
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file: RegFile,
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) {
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// The default for predicates is true
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let true_reg = RegRef::new(file, 7, 1);
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let (not, reg) = match src.src_ref {
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SrcRef::True => (false, true_reg),
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SrcRef::False => (true, true_reg),
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SrcRef::Reg(reg) => {
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assert!(reg.file() == file);
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(false, reg)
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}
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_ => panic!("Not a register"),
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};
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self.set_pred_reg(range, reg);
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self.set_bit(not_bit, not ^ src_mod_is_bnot(src.src_mod));
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}
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fn set_pred_src(&mut self, range: Range<usize>, not_bit: usize, src: Src) {
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self.set_pred_src_file(range, not_bit, src, RegFile::Pred);
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}
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fn set_upred_src(&mut self, range: Range<usize>, not_bit: usize, src: Src) {
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self.set_pred_src_file(range, not_bit, src, RegFile::UPred);
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}
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fn set_src_cb(&mut self, range: Range<usize>, cx_bit: usize, cb: &CBufRef) {
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let mut v = BitMutView::new_subset(self, range);
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v.set_field(6..22, cb.offset);
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match cb.buf {
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CBuf::Binding(idx) => {
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v.set_field(22..27, idx);
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self.set_bit(cx_bit, false);
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}
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CBuf::BindlessUGPR(reg) => {
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assert!(reg.base_idx() <= 63);
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assert!(reg.file() == RegFile::UGPR);
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v.set_field(0..6, reg.base_idx());
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self.set_bit(cx_bit, true);
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}
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CBuf::BindlessSSA(_) => panic!("SSA values must be lowered"),
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}
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}
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fn set_pred(&mut self, pred: &Pred) {
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assert!(!pred.is_false());
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self.set_pred_reg(
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12..15,
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match pred.pred_ref {
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PredRef::None => RegRef::zero(RegFile::Pred, 1),
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PredRef::Reg(reg) => reg,
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PredRef::SSA(_) => panic!("SSA values must be lowered"),
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},
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);
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self.set_bit(15, pred.pred_inv);
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}
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fn set_dst(&mut self, dst: Dst) {
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match dst {
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Dst::None => self.set_reg(16..24, RegRef::zero(RegFile::GPR, 1)),
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Dst::Reg(reg) => self.set_reg(16..24, reg),
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_ => panic!("Not a register"),
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}
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}
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fn set_udst(&mut self, dst: Dst) {
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match dst {
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Dst::None => self.set_ureg(16..24, RegRef::zero(RegFile::UGPR, 1)),
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Dst::Reg(reg) => self.set_ureg(16..24, reg),
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_ => panic!("Not a register"),
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}
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}
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fn set_bar_reg(&mut self, range: Range<usize>, reg: RegRef) {
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assert!(range.len() == 4);
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assert!(reg.file() == RegFile::Bar);
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assert!(reg.comps() == 1);
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self.set_field(range, reg.base_idx());
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}
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fn set_bar_dst(&mut self, range: Range<usize>, dst: Dst) {
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self.set_bar_reg(range, *dst.as_reg().unwrap());
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}
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fn set_bar_src(&mut self, range: Range<usize>, src: Src) {
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assert!(src.src_mod.is_none());
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self.set_bar_reg(range, *src.src_ref.as_reg().unwrap());
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}
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fn set_instr_deps(&mut self, deps: &InstrDeps) {
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self.set_field(105..109, deps.delay);
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self.set_bit(109, deps.yld);
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self.set_field(110..113, deps.wr_bar().unwrap_or(7));
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self.set_field(113..116, deps.rd_bar().unwrap_or(7));
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self.set_field(116..122, deps.wt_bar_mask);
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self.set_field(122..126, deps.reuse_mask);
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}
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}
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//
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// Helpers for encoding of ALU instructions
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//
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struct ALURegRef {
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pub reg: RegRef,
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pub abs: bool,
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@ -226,178 +409,7 @@ impl ALUSrc {
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}
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}
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struct SM70Encoder<'a> {
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sm: &'a ShaderModel70,
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ip: usize,
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labels: &'a HashMap<Label, usize>,
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inst: [u32; 4],
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}
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impl BitViewable for SM70Encoder<'_> {
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fn bits(&self) -> usize {
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BitView::new(&self.inst).bits()
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}
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fn get_bit_range_u64(&self, range: Range<usize>) -> u64 {
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BitView::new(&self.inst).get_bit_range_u64(range)
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}
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}
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impl BitMutViewable for SM70Encoder<'_> {
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fn set_bit_range_u64(&mut self, range: Range<usize>, val: u64) {
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BitMutView::new(&mut self.inst).set_bit_range_u64(range, val);
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}
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}
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impl SetFieldU64 for SM70Encoder<'_> {
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fn set_field_u64(&mut self, range: Range<usize>, val: u64) {
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BitMutView::new(&mut self.inst).set_field_u64(range, val);
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}
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}
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impl SM70Encoder<'_> {
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fn set_bit(&mut self, bit: usize, val: bool) {
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BitMutView::new(&mut self.inst).set_bit(bit, val);
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}
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fn set_reg(&mut self, range: Range<usize>, reg: RegRef) {
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assert!(range.len() == 8);
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assert!(reg.file() == RegFile::GPR);
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self.set_field(range, reg.base_idx());
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}
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fn set_ureg(&mut self, range: Range<usize>, reg: RegRef) {
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assert!(self.sm.sm >= 75);
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assert!(range.len() == 8);
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assert!(reg.file() == RegFile::UGPR);
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assert!(reg.base_idx() <= 63);
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self.set_field(range, reg.base_idx());
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}
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fn set_pred_reg(&mut self, range: Range<usize>, reg: RegRef) {
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assert!(range.len() == 3);
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assert!(reg.base_idx() <= 7);
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assert!(reg.comps() == 1);
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self.set_field(range, reg.base_idx());
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}
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fn set_reg_src(&mut self, range: Range<usize>, src: Src) {
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assert!(src.src_mod.is_none());
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match src.src_ref {
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SrcRef::Zero => self.set_reg(range, RegRef::zero(RegFile::GPR, 1)),
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SrcRef::Reg(reg) => self.set_reg(range, reg),
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_ => panic!("Not a register"),
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}
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}
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fn set_pred_dst(&mut self, range: Range<usize>, dst: Dst) {
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match dst {
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Dst::None => {
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self.set_pred_reg(range, RegRef::zero(RegFile::Pred, 1));
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}
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Dst::Reg(reg) => self.set_pred_reg(range, reg),
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_ => panic!("Not a register"),
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}
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}
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fn set_pred_src_file(
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&mut self,
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range: Range<usize>,
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not_bit: usize,
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src: Src,
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file: RegFile,
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) {
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// The default for predicates is true
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let true_reg = RegRef::new(file, 7, 1);
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let (not, reg) = match src.src_ref {
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SrcRef::True => (false, true_reg),
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SrcRef::False => (true, true_reg),
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SrcRef::Reg(reg) => {
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assert!(reg.file() == file);
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(false, reg)
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}
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_ => panic!("Not a register"),
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};
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self.set_pred_reg(range, reg);
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self.set_bit(not_bit, not ^ src_mod_is_bnot(src.src_mod));
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}
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fn set_pred_src(&mut self, range: Range<usize>, not_bit: usize, src: Src) {
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self.set_pred_src_file(range, not_bit, src, RegFile::Pred);
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}
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fn set_upred_src(&mut self, range: Range<usize>, not_bit: usize, src: Src) {
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self.set_pred_src_file(range, not_bit, src, RegFile::UPred);
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}
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fn set_src_cb(&mut self, range: Range<usize>, cx_bit: usize, cb: &CBufRef) {
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let mut v = BitMutView::new_subset(self, range);
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v.set_field(6..22, cb.offset);
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match cb.buf {
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CBuf::Binding(idx) => {
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v.set_field(22..27, idx);
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self.set_bit(cx_bit, false);
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}
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CBuf::BindlessUGPR(reg) => {
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assert!(reg.base_idx() <= 63);
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assert!(reg.file() == RegFile::UGPR);
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v.set_field(0..6, reg.base_idx());
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self.set_bit(cx_bit, true);
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}
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CBuf::BindlessSSA(_) => panic!("SSA values must be lowered"),
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}
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}
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fn set_opcode(&mut self, opcode: u16) {
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self.set_field(0..12, opcode);
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}
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fn set_pred(&mut self, pred: &Pred) {
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assert!(!pred.is_false());
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self.set_pred_reg(
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12..15,
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match pred.pred_ref {
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PredRef::None => RegRef::zero(RegFile::Pred, 1),
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PredRef::Reg(reg) => reg,
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PredRef::SSA(_) => panic!("SSA values must be lowered"),
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},
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);
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self.set_bit(15, pred.pred_inv);
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}
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fn set_dst(&mut self, dst: Dst) {
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match dst {
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Dst::None => self.set_reg(16..24, RegRef::zero(RegFile::GPR, 1)),
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Dst::Reg(reg) => self.set_reg(16..24, reg),
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_ => panic!("Not a register"),
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}
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}
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fn set_udst(&mut self, dst: Dst) {
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match dst {
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Dst::None => self.set_ureg(16..24, RegRef::zero(RegFile::UGPR, 1)),
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Dst::Reg(reg) => self.set_ureg(16..24, reg),
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_ => panic!("Not a register"),
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}
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}
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fn set_bar_reg(&mut self, range: Range<usize>, reg: RegRef) {
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assert!(range.len() == 4);
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assert!(reg.file() == RegFile::Bar);
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assert!(reg.comps() == 1);
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self.set_field(range, reg.base_idx());
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}
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fn set_bar_dst(&mut self, range: Range<usize>, dst: Dst) {
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self.set_bar_reg(range, *dst.as_reg().unwrap());
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}
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fn set_bar_src(&mut self, range: Range<usize>, src: Src) {
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assert!(src.src_mod.is_none());
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self.set_bar_reg(range, *src.src_ref.as_reg().unwrap());
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}
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fn set_swizzle(&mut self, range: Range<usize>, swizzle: SrcSwizzle) {
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assert!(range.len() == 2);
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@ -688,15 +700,6 @@ impl SM70Encoder<'_> {
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self.set_field(9..12, form);
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}
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fn set_instr_deps(&mut self, deps: &InstrDeps) {
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self.set_field(105..109, deps.delay);
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self.set_bit(109, deps.yld);
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self.set_field(110..113, deps.wr_bar().unwrap_or(7));
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self.set_field(113..116, deps.rd_bar().unwrap_or(7));
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self.set_field(116..122, deps.wt_bar_mask);
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self.set_field(122..126, deps.reuse_mask);
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}
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fn set_rnd_mode(&mut self, range: Range<usize>, rnd_mode: FRndMode) {
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assert!(range.len() == 2);
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self.set_field(
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@ -711,6 +714,10 @@ impl SM70Encoder<'_> {
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}
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}
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//
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// Implementations of SM70Op for each op we support on Volta+
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//
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impl SM70Op for OpFAdd {
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fn encode(&self, e: &mut SM70Encoder<'_>) {
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if src_is_zero_or_gpr(&self.srcs[1]) {
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