From 1b594e6745d57cf150b250600c74ac36a40f44f8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Mon, 26 May 2025 04:33:37 -0400 Subject: [PATCH] radeonsi: gather nr_pos_exports from the final NIR MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Acked-by: Timur Kristóf Part-of: --- src/gallium/drivers/radeonsi/si_shader.c | 30 ++----------------- .../drivers/radeonsi/si_shader_variant_info.c | 29 +++++++++++++----- 2 files changed, 23 insertions(+), 36 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c index e7b5390a2a2..3459269223b 100644 --- a/src/gallium/drivers/radeonsi/si_shader.c +++ b/src/gallium/drivers/radeonsi/si_shader.c @@ -1286,30 +1286,6 @@ static void si_assign_param_offsets(nir_shader *nir, struct si_shader *shader, } } -static unsigned si_get_nr_pos_exports(const struct si_shader *shader) -{ - const struct si_shader_info *info = &shader->selector->info; - - /* Must have a position export. */ - unsigned nr_pos_exports = 1; - - if ((info->writes_psize && !shader->key.ge.opt.kill_pointsize) || - (info->writes_edgeflag && !shader->key.ge.as_ngg) || - (info->writes_layer && !shader->key.ge.opt.kill_layer) || - info->writes_viewport_index || shader->selector->screen->options.vrs2x2) { - nr_pos_exports++; - } - - unsigned clipdist_mask = shader->info.clipdist_mask | shader->info.culldist_mask; - - for (int i = 0; i < 2; i++) { - if (clipdist_mask & BITFIELD_RANGE(i * 4, 4)) - nr_pos_exports++; - } - - return nr_pos_exports; -} - bool si_should_clear_lds(struct si_screen *sscreen, const struct nir_shader *shader) { return gl_shader_stage_is_compute(shader->info.stage) && @@ -1549,9 +1525,6 @@ static void run_late_optimization_and_lowering_passes(struct si_nir_shader_ctx * /* Assign param export indices. */ si_assign_param_offsets(nir, shader, &ctx->temp_info); - /* Assign num of position exports. */ - shader->info.nr_pos_exports = si_get_nr_pos_exports(shader); - if (key->ge.as_ngg) { /* Lower last VGT NGG shader stage. */ si_lower_ngg(shader, nir, &ctx->temp_info); @@ -1875,7 +1848,6 @@ si_nir_generate_gs_copy_shader(struct si_screen *sscreen, shader->is_gs_copy_shader = true; shader->wave_size = si_determine_wave_size(sscreen, shader); shader->info.num_streamout_vec4s = gs_shader->info.num_streamout_vec4s; - shader->info.nr_pos_exports = si_get_nr_pos_exports(gs_shader); shader->info.nr_param_exports = gs_shader->info.nr_param_exports; shader->info.clipdist_mask = gs_shader->info.clipdist_mask; shader->info.culldist_mask = gs_shader->info.culldist_mask; @@ -1895,6 +1867,8 @@ si_nir_generate_gs_copy_shader(struct si_screen *sscreen, si_nir_opts(gs_selector->screen, nir, false); NIR_PASS_V(nir, nir_lower_load_const_to_scalar); + /* This pass must be last. */ + si_get_late_shader_variant_info(shader, &linked.consumer.args, nir); if (si_can_dump_shader(sscreen, MESA_SHADER_GEOMETRY, SI_DUMP_NIR)) { fprintf(stderr, "GS Copy Shader:\n"); diff --git a/src/gallium/drivers/radeonsi/si_shader_variant_info.c b/src/gallium/drivers/radeonsi/si_shader_variant_info.c index 6ebd7946619..8ff58e69173 100644 --- a/src/gallium/drivers/radeonsi/si_shader_variant_info.c +++ b/src/gallium/drivers/radeonsi/si_shader_variant_info.c @@ -271,16 +271,18 @@ void si_get_shader_variant_info(struct si_shader *shader, void si_get_late_shader_variant_info(struct si_shader *shader, struct si_shader_args *args, nir_shader *nir) { - if ((nir->info.stage != MESA_SHADER_VERTEX || nir->info.vs.blit_sgprs_amd) && - nir->info.stage != MESA_SHADER_TESS_EVAL && - (nir->info.stage != MESA_SHADER_GEOMETRY || !shader->key.ge.as_ngg)) - return; - nir_foreach_block(block, nir_shader_get_entrypoint(nir)) { nir_foreach_instr(instr, block) { - if (instr->type == nir_instr_type_intrinsic && - nir_instr_as_intrinsic(instr)->intrinsic == nir_intrinsic_load_scalar_arg_amd && - nir_intrinsic_base(nir_instr_as_intrinsic(instr)) == args->vs_state_bits.arg_index) { + if (instr->type != nir_instr_type_intrinsic) + continue; + + nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr); + switch (intr->intrinsic) { + case nir_intrinsic_load_scalar_arg_amd: + if (!args->vs_state_bits.used || + nir_intrinsic_base(intr) != args->vs_state_bits.arg_index) + continue; + assert(args->vs_state_bits.used); /* Gather which VS_STATE and GS_STATE user SGPR bits are used. */ @@ -297,6 +299,17 @@ void si_get_late_shader_variant_info(struct si_shader *shader, struct si_shader_ if (bits_used & ENCODE_FIELD(GS_STATE_OUTPRIM, ~0)) shader->info.uses_gs_state_outprim = true; } + break; + case nir_intrinsic_export_amd: { + unsigned target = nir_intrinsic_base(intr); + if (target >= V_008DFC_SQ_EXP_POS && target <= V_008DFC_SQ_EXP_POS + 4) { + shader->info.nr_pos_exports = MAX2(shader->info.nr_pos_exports, + target - V_008DFC_SQ_EXP_POS + 1); + } + break; + } + default: + break; } } }