fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-02-18 01:50:40 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions 3

freedreno,tu,ir3: DCE ij_pix

Browse source 
SP_FS_PREFETCH_CNTL.IJ_WRITE_DISABLE allows disabling ij write, so
now we could DCE it.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19652>
This commit is contained in:
Danylo Piliaiev 2022-11-10 15:40:48 +01:00 • committed by Marge Bot
parent c7c186590c
commit 1b492d5031
3 changed files with 6 additions and 16 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

7
src/freedreno/ir3/ir3_dce.c
View file

@ -112,13 +112,6 @@ find_and_remove_unused(struct ir3 *ir, struct ir3_shader_variant *so)
foreach_block (block, &ir->block_list) {
foreach_instr (instr, &block->instr_list) {
if (instr->opc == OPC_META_INPUT) {
/* special case, if pre-fs texture fetch used, we cannot
* eliminate the barycentric i/j input
*/
if (so->num_sampler_prefetch &&
instr->input.sysval == SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL)
continue;
/* Without GS header geometry shader is never invoked. */
if (instr->input.sysval == SYSTEM_VALUE_GS_HEADER_IR3)
continue;

6
src/freedreno/vulkan/tu_pipeline.c
View file

@ -1498,9 +1498,9 @@ tu6_emit_fs_inputs(struct tu_cs *cs, const struct ir3_shader_variant *fs)
ij_regid[i] = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL + i);
if (fs->num_sampler_prefetch > 0) {
assert(VALIDREG(ij_regid[IJ_PERSP_PIXEL]));
/* also, it seems like ij_pix is *required* to be r0.x */
assert(ij_regid[IJ_PERSP_PIXEL] == regid(0, 0));
/* It seems like ij_pix is *required* to be r0.x */
assert(!VALIDREG(ij_regid[IJ_PERSP_PIXEL]) ||
ij_regid[IJ_PERSP_PIXEL] == regid(0, 0));
}
tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_PREFETCH_CNTL, 1 + fs->num_sampler_prefetch);

9
src/gallium/drivers/freedreno/a6xx/fd6_program.c
View file

@ -526,13 +526,10 @@ setup_stateobj(struct fd_ringbuffer *ring, struct fd_context *ctx,
ij_regid[i] =
ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL + i);
/* If we have pre-dispatch texture fetches, then ij_pix should not
* be DCE'd, even if not actually used in the shader itself:
*/
if (fs->num_sampler_prefetch > 0) {
assert(VALIDREG(ij_regid[IJ_PERSP_PIXEL]));
/* also, it seems like ij_pix is *required* to be r0.x */
assert(ij_regid[IJ_PERSP_PIXEL] == regid(0, 0));
/* It seems like ij_pix is *required* to be r0.x */
assert(!VALIDREG(ij_regid[IJ_PERSP_PIXEL]) ||
ij_regid[IJ_PERSP_PIXEL] == regid(0, 0));
}
/* we can't write gl_SampleMask for !msaa.. if b0 is zero then we