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https://gitlab.freedesktop.org/mesa/mesa.git
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nak/sm70: Defer ALU src processing until encode_alu()
This makes encode_alu() take Option<&Src> and call ALUSrc::from_src() itself. This is necessary for handling uniform ALU correctly as we can't actually separate Reg from UReg without knowing what kind of ALU op we are. While we're here, take an Option<&Dst> instead of Option<Dst>. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29591>
This commit is contained in:
Faith Ekstrand
Marge Bot
parent
e244f7bb44
commit
1ae83135af
1 changed files with 172 additions and 260 deletions
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@ -60,7 +60,11 @@ fn dst_is_bar(dst: Dst) -> bool {
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}
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impl ALUSrc {
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fn from_src_file(src: &Src, file: RegFile) -> ALUSrc {
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fn from_src_file(src: Option<&Src>, file: RegFile) -> ALUSrc {
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let Some(src) = src else {
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return ALUSrc::None;
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};
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match src.src_ref {
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SrcRef::Zero | SrcRef::Reg(_) => {
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let reg = match src.src_ref {
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@ -100,16 +104,10 @@ impl ALUSrc {
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}
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}
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pub fn from_src(src: &Src) -> ALUSrc {
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pub fn from_src(src: Option<&Src>) -> ALUSrc {
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ALUSrc::from_src_file(src, RegFile::GPR)
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}
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#[allow(dead_code)]
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pub fn from_usrc(src: &Src) -> ALUSrc {
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assert!(src.is_uniform());
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ALUSrc::from_src_file(src, RegFile::UGPR)
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}
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pub fn has_src_mod(&self) -> bool {
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match self {
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ALUSrc::Reg(reg) | ALUSrc::UReg(reg) => reg.abs || reg.neg,
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@ -405,16 +403,20 @@ impl SM70Instr {
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fn encode_alu_base(
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&mut self,
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opcode: u16,
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dst: Option<Dst>,
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src0: ALUSrc,
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src1: ALUSrc,
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src2: ALUSrc,
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dst: Option<&Dst>,
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src0: Option<&Src>,
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src1: Option<&Src>,
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src2: Option<&Src>,
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is_fp16_alu: bool,
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) {
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if let Some(dst) = dst {
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self.set_dst(dst);
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self.set_dst(*dst);
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}
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let src0 = ALUSrc::from_src(src0);
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let src1 = ALUSrc::from_src(src1);
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let src2 = ALUSrc::from_src(src2);
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// Bits 74..76 are used both for the swizzle on src0 and for the source
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// modifier for the register source of src1 and src2. When both are
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// registers, it's used for src2. The hardware elects to always support
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@ -539,10 +541,10 @@ impl SM70Instr {
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fn encode_alu(
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&mut self,
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opcode: u16,
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dst: Option<Dst>,
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src0: ALUSrc,
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src1: ALUSrc,
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src2: ALUSrc,
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dst: Option<&Dst>,
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src0: Option<&Src>,
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src1: Option<&Src>,
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src2: Option<&Src>,
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) {
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self.encode_alu_base(opcode, dst, src0, src1, src2, false);
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}
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@ -550,10 +552,10 @@ impl SM70Instr {
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fn encode_fp16_alu(
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&mut self,
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opcode: u16,
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dst: Option<Dst>,
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src0: ALUSrc,
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src1: ALUSrc,
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src2: ALUSrc,
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dst: Option<&Dst>,
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src0: Option<&Src>,
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src1: Option<&Src>,
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src2: Option<&Src>,
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) {
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self.encode_alu_base(opcode, dst, src0, src1, src2, true);
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}
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@ -584,18 +586,18 @@ impl SM70Instr {
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if op.srcs[1].src_ref.as_reg().is_some() {
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self.encode_alu(
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0x021,
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Some(op.dst),
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ALUSrc::from_src(&op.srcs[0]),
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ALUSrc::from_src(&op.srcs[1]),
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ALUSrc::None,
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Some(&op.dst),
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Some(&op.srcs[0]),
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Some(&op.srcs[1]),
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None,
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);
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} else {
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self.encode_alu(
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0x021,
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Some(op.dst),
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ALUSrc::from_src(&op.srcs[0]),
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ALUSrc::from_src(&Src::new_zero()),
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ALUSrc::from_src(&op.srcs[1]),
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Some(&op.dst),
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Some(&op.srcs[0]),
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Some(&Src::new_zero()),
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Some(&op.srcs[1]),
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);
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}
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self.set_bit(77, op.saturate);
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@ -606,10 +608,10 @@ impl SM70Instr {
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fn encode_ffma(&mut self, op: &OpFFma) {
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self.encode_alu(
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0x023,
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Some(op.dst),
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ALUSrc::from_src(&op.srcs[0]),
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ALUSrc::from_src(&op.srcs[1]),
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ALUSrc::from_src(&op.srcs[2]),
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Some(&op.dst),
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Some(&op.srcs[0]),
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Some(&op.srcs[1]),
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Some(&op.srcs[2]),
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);
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self.set_bit(76, op.dnz);
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self.set_bit(77, op.saturate);
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@ -620,10 +622,10 @@ impl SM70Instr {
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fn encode_fmnmx(&mut self, op: &OpFMnMx) {
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self.encode_alu(
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0x009,
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Some(op.dst),
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ALUSrc::from_src(&op.srcs[0]),
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ALUSrc::from_src(&op.srcs[1]),
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ALUSrc::from_src(&Src::new_zero()),
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Some(&op.dst),
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Some(&op.srcs[0]),
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Some(&op.srcs[1]),
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Some(&Src::new_zero()),
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);
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self.set_pred_src(87..90, 90, op.min);
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self.set_bit(80, op.ftz);
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@ -632,10 +634,10 @@ impl SM70Instr {
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fn encode_fmul(&mut self, op: &OpFMul) {
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self.encode_alu(
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0x020,
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Some(op.dst),
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ALUSrc::from_src(&op.srcs[0]),
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ALUSrc::from_src(&op.srcs[1]),
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ALUSrc::from_src(&Src::new_zero()),
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Some(&op.dst),
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Some(&op.srcs[0]),
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Some(&op.srcs[1]),
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Some(&Src::new_zero()),
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);
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self.set_bit(76, op.dnz);
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self.set_bit(77, op.saturate);
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@ -670,10 +672,10 @@ impl SM70Instr {
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fn encode_fset(&mut self, op: &OpFSet) {
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self.encode_alu(
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0x00a,
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Some(op.dst),
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ALUSrc::from_src(&op.srcs[0]),
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ALUSrc::from_src(&op.srcs[1]),
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ALUSrc::None,
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Some(&op.dst),
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Some(&op.srcs[0]),
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Some(&op.srcs[1]),
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None,
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);
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self.set_float_cmp_op(76..80, op.cmp_op);
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self.set_bit(80, op.ftz);
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@ -696,9 +698,9 @@ impl SM70Instr {
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self.encode_alu(
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0x00b,
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None,
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ALUSrc::from_src(&op.srcs[0]),
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ALUSrc::from_src(&op.srcs[1]),
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ALUSrc::None,
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Some(&op.srcs[0]),
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Some(&op.srcs[1]),
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None,
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);
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self.set_pred_set_op(74..76, op.set_op);
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@ -739,13 +741,7 @@ impl SM70Instr {
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}
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fn encode_mufu(&mut self, op: &OpMuFu) {
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self.encode_alu(
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0x108,
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Some(op.dst),
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ALUSrc::None,
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ALUSrc::from_src(&op.src),
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ALUSrc::None,
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);
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self.encode_alu(0x108, Some(&op.dst), None, Some(&op.src), None);
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self.set_field(
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74..80,
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match op.op {
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@ -766,10 +762,10 @@ impl SM70Instr {
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fn encode_dadd(&mut self, op: &OpDAdd) {
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self.encode_alu(
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0x029,
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Some(op.dst),
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ALUSrc::from_src(&op.srcs[0]),
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ALUSrc::None,
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ALUSrc::from_src(&op.srcs[1]),
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Some(&op.dst),
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Some(&op.srcs[0]),
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None,
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Some(&op.srcs[1]),
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);
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self.set_rnd_mode(78..80, op.rnd_mode);
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}
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@ -777,10 +773,10 @@ impl SM70Instr {
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fn encode_dfma(&mut self, op: &OpDFma) {
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self.encode_alu(
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0x02b,
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Some(op.dst),
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ALUSrc::from_src(&op.srcs[0]),
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ALUSrc::from_src(&op.srcs[1]),
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ALUSrc::from_src(&op.srcs[2]),
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Some(&op.dst),
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Some(&op.srcs[0]),
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Some(&op.srcs[1]),
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Some(&op.srcs[2]),
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);
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self.set_rnd_mode(78..80, op.rnd_mode);
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}
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@ -788,10 +784,10 @@ impl SM70Instr {
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fn encode_dmul(&mut self, op: &OpDMul) {
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self.encode_alu(
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0x028,
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Some(op.dst),
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ALUSrc::from_src(&op.srcs[0]),
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ALUSrc::from_src(&op.srcs[1]),
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ALUSrc::None,
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Some(&op.dst),
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Some(&op.srcs[0]),
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Some(&op.srcs[1]),
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None,
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);
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self.set_rnd_mode(78..80, op.rnd_mode);
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}
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@ -802,18 +798,18 @@ impl SM70Instr {
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self.encode_alu(
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0x02a,
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None,
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ALUSrc::from_src(&op.srcs[0]),
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ALUSrc::from_src(&op.srcs[1]),
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ALUSrc::None,
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Some(&op.srcs[0]),
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Some(&op.srcs[1]),
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None,
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);
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}
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_ => {
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self.encode_alu(
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0x02a,
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None,
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ALUSrc::from_src(&op.srcs[0]),
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ALUSrc::None,
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ALUSrc::from_src(&op.srcs[1]),
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Some(&op.srcs[0]),
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None,
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Some(&op.srcs[1]),
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);
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}
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}
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@ -832,19 +828,19 @@ impl SM70Instr {
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SrcRef::Reg(_) | SrcRef::Zero => {
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self.encode_fp16_alu(
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0x030,
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Some(op.dst),
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ALUSrc::from_src(&op.srcs[0]),
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ALUSrc::from_src(&op.srcs[1]),
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ALUSrc::None,
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Some(&op.dst),
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Some(&op.srcs[0]),
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Some(&op.srcs[1]),
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None,
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);
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}
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_ => {
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self.encode_fp16_alu(
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0x030,
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Some(op.dst),
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ALUSrc::from_src(&op.srcs[0]),
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ALUSrc::None,
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ALUSrc::from_src(&op.srcs[1]),
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Some(&op.dst),
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Some(&op.srcs[0]),
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None,
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Some(&op.srcs[1]),
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);
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}
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}
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@ -861,10 +857,10 @@ impl SM70Instr {
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self.encode_fp16_alu(
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0x031,
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Some(op.dst),
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ALUSrc::from_src(&op.srcs[0]),
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ALUSrc::from_src(&op.srcs[1]),
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ALUSrc::from_src(&op.srcs[2]),
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Some(&op.dst),
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Some(&op.srcs[0]),
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Some(&op.srcs[1]),
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Some(&op.srcs[2]),
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);
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self.set_bit(76, op.dnz);
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@ -878,10 +874,10 @@ impl SM70Instr {
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fn encode_hmul2(&mut self, op: &OpHMul2) {
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self.encode_fp16_alu(
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0x032,
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Some(op.dst),
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ALUSrc::from_src(&op.srcs[0]),
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ALUSrc::from_src(&op.srcs[1]),
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ALUSrc::None,
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Some(&op.dst),
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Some(&op.srcs[0]),
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Some(&op.srcs[1]),
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None,
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);
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self.set_bit(76, op.dnz);
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@ -897,19 +893,19 @@ impl SM70Instr {
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SrcRef::Reg(_) | SrcRef::Zero => {
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self.encode_fp16_alu(
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0x033,
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Some(op.dst),
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ALUSrc::from_src(&op.srcs[0]),
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ALUSrc::from_src(&op.srcs[1]),
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ALUSrc::None,
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Some(&op.dst),
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Some(&op.srcs[0]),
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Some(&op.srcs[1]),
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None,
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);
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}
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_ => {
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self.encode_fp16_alu(
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0x033,
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Some(op.dst),
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ALUSrc::from_src(&op.srcs[0]),
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ALUSrc::None,
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ALUSrc::from_src(&op.srcs[1]),
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Some(&op.dst),
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Some(&op.srcs[0]),
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None,
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Some(&op.srcs[1]),
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);
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}
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}
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@ -931,18 +927,18 @@ impl SM70Instr {
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self.encode_fp16_alu(
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0x034,
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None,
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ALUSrc::from_src(&op.srcs[0]),
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ALUSrc::from_src(&op.srcs[1]),
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ALUSrc::None,
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Some(&op.srcs[0]),
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Some(&op.srcs[1]),
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None,
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);
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}
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_ => {
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self.encode_fp16_alu(
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0x034,
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None,
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ALUSrc::from_src(&op.srcs[0]),
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ALUSrc::None,
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ALUSrc::from_src(&op.srcs[1]),
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Some(&op.srcs[0]),
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None,
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Some(&op.srcs[1]),
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);
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}
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}
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|
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@ -964,10 +960,10 @@ impl SM70Instr {
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self.encode_fp16_alu(
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0x040,
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Some(op.dst),
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ALUSrc::from_src(&op.srcs[0]),
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ALUSrc::from_src(&op.srcs[1]),
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ALUSrc::None,
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Some(&op.dst),
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Some(&op.srcs[0]),
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Some(&op.srcs[1]),
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None,
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);
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// This differentiate between integer and fp16 output
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|
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@ -983,33 +979,21 @@ impl SM70Instr {
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fn encode_bmsk(&mut self, op: &OpBMsk) {
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self.encode_alu(
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0x01b,
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Some(op.dst),
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ALUSrc::from_src(&op.pos),
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ALUSrc::from_src(&op.width),
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ALUSrc::None,
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Some(&op.dst),
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Some(&op.pos),
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Some(&op.width),
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None,
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);
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self.set_bit(75, op.wrap);
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}
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fn encode_brev(&mut self, op: &OpBRev) {
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self.encode_alu(
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0x101,
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Some(op.dst),
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ALUSrc::None,
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ALUSrc::from_src(&op.src),
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ALUSrc::None,
|
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);
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self.encode_alu(0x101, Some(&op.dst), None, Some(&op.src), None);
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}
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fn encode_flo(&mut self, op: &OpFlo) {
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self.encode_alu(
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0x100,
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Some(op.dst),
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ALUSrc::None,
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ALUSrc::from_src(&op.src),
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ALUSrc::None,
|
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);
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self.encode_alu(0x100, Some(&op.dst), None, Some(&op.src), None);
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self.set_pred_dst(81..84, Dst::None);
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self.set_field(74..75, op.return_shift_amount as u8);
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self.set_field(73..74, op.signed as u8);
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|
|
@ -1018,13 +1002,7 @@ impl SM70Instr {
|
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}
|
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fn encode_iabs(&mut self, op: &OpIAbs) {
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self.encode_alu(
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0x013,
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Some(op.dst),
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ALUSrc::None,
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ALUSrc::from_src(&op.src),
|
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ALUSrc::None,
|
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);
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self.encode_alu(0x013, Some(&op.dst), None, Some(&op.src), None);
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}
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|
||||
fn encode_iadd3(&mut self, op: &OpIAdd3) {
|
||||
|
|
@ -1033,10 +1011,10 @@ impl SM70Instr {
|
|||
|
||||
self.encode_alu(
|
||||
0x010,
|
||||
Some(op.dst),
|
||||
ALUSrc::from_src(&op.srcs[0]),
|
||||
ALUSrc::from_src(&op.srcs[1]),
|
||||
ALUSrc::from_src(&op.srcs[2]),
|
||||
Some(&op.dst),
|
||||
Some(&op.srcs[0]),
|
||||
Some(&op.srcs[1]),
|
||||
Some(&op.srcs[2]),
|
||||
);
|
||||
|
||||
self.set_pred_src(87..90, 90, false.into());
|
||||
|
|
@ -1052,10 +1030,10 @@ impl SM70Instr {
|
|||
|
||||
self.encode_alu(
|
||||
0x010,
|
||||
Some(op.dst),
|
||||
ALUSrc::from_src(&op.srcs[0]),
|
||||
ALUSrc::from_src(&op.srcs[1]),
|
||||
ALUSrc::from_src(&op.srcs[2]),
|
||||
Some(&op.dst),
|
||||
Some(&op.srcs[0]),
|
||||
Some(&op.srcs[1]),
|
||||
Some(&op.srcs[2]),
|
||||
);
|
||||
|
||||
self.set_bit(74, true); // .X
|
||||
|
|
@ -1070,10 +1048,10 @@ impl SM70Instr {
|
|||
fn encode_idp4(&mut self, op: &OpIDp4) {
|
||||
self.encode_alu(
|
||||
0x026,
|
||||
Some(op.dst),
|
||||
ALUSrc::from_src(&op.srcs[0]),
|
||||
ALUSrc::from_src(&op.srcs[1]),
|
||||
ALUSrc::from_src(&op.srcs[2]),
|
||||
Some(&op.dst),
|
||||
Some(&op.srcs[0]),
|
||||
Some(&op.srcs[1]),
|
||||
Some(&op.srcs[2]),
|
||||
);
|
||||
|
||||
self.set_bit(
|
||||
|
|
@ -1097,10 +1075,10 @@ impl SM70Instr {
|
|||
fn encode_imad(&mut self, op: &OpIMad) {
|
||||
self.encode_alu(
|
||||
0x024,
|
||||
Some(op.dst),
|
||||
ALUSrc::from_src(&op.srcs[0]),
|
||||
ALUSrc::from_src(&op.srcs[1]),
|
||||
ALUSrc::from_src(&op.srcs[2]),
|
||||
Some(&op.dst),
|
||||
Some(&op.srcs[0]),
|
||||
Some(&op.srcs[1]),
|
||||
Some(&op.srcs[2]),
|
||||
);
|
||||
self.set_pred_dst(81..84, Dst::None);
|
||||
self.set_bit(73, op.signed);
|
||||
|
|
@ -1109,10 +1087,10 @@ impl SM70Instr {
|
|||
fn encode_imad64(&mut self, op: &OpIMad64) {
|
||||
self.encode_alu(
|
||||
0x025,
|
||||
Some(op.dst),
|
||||
ALUSrc::from_src(&op.srcs[0]),
|
||||
ALUSrc::from_src(&op.srcs[1]),
|
||||
ALUSrc::from_src(&op.srcs[2]),
|
||||
Some(&op.dst),
|
||||
Some(&op.srcs[0]),
|
||||
Some(&op.srcs[1]),
|
||||
Some(&op.srcs[2]),
|
||||
);
|
||||
self.set_pred_dst(81..84, Dst::None);
|
||||
self.set_bit(73, op.signed);
|
||||
|
|
@ -1121,10 +1099,10 @@ impl SM70Instr {
|
|||
fn encode_imnmx(&mut self, op: &OpIMnMx) {
|
||||
self.encode_alu(
|
||||
0x017,
|
||||
Some(op.dst),
|
||||
ALUSrc::from_src(&op.srcs[0]),
|
||||
ALUSrc::from_src(&op.srcs[1]),
|
||||
ALUSrc::None,
|
||||
Some(&op.dst),
|
||||
Some(&op.srcs[0]),
|
||||
Some(&op.srcs[1]),
|
||||
None,
|
||||
);
|
||||
self.set_pred_src(87..90, 90, op.min);
|
||||
self.set_bit(
|
||||
|
|
@ -1155,9 +1133,9 @@ impl SM70Instr {
|
|||
self.encode_alu(
|
||||
0x00c,
|
||||
None,
|
||||
ALUSrc::from_src(&op.srcs[0]),
|
||||
ALUSrc::from_src(&op.srcs[1]),
|
||||
ALUSrc::None,
|
||||
Some(&op.srcs[0]),
|
||||
Some(&op.srcs[1]),
|
||||
None,
|
||||
);
|
||||
|
||||
self.set_pred_src(68..71, 71, op.low_cmp);
|
||||
|
|
@ -1182,10 +1160,10 @@ impl SM70Instr {
|
|||
fn encode_lop3(&mut self, op: &OpLop3) {
|
||||
self.encode_alu(
|
||||
0x012,
|
||||
Some(op.dst),
|
||||
ALUSrc::from_src(&op.srcs[0]),
|
||||
ALUSrc::from_src(&op.srcs[1]),
|
||||
ALUSrc::from_src(&op.srcs[2]),
|
||||
Some(&op.dst),
|
||||
Some(&op.srcs[0]),
|
||||
Some(&op.srcs[1]),
|
||||
Some(&op.srcs[2]),
|
||||
);
|
||||
|
||||
self.set_field(72..80, op.op.lut);
|
||||
|
|
@ -1195,13 +1173,7 @@ impl SM70Instr {
|
|||
}
|
||||
|
||||
fn encode_popc(&mut self, op: &OpPopC) {
|
||||
self.encode_alu(
|
||||
0x109,
|
||||
Some(op.dst),
|
||||
ALUSrc::None,
|
||||
ALUSrc::from_src(&op.src),
|
||||
ALUSrc::None,
|
||||
);
|
||||
self.encode_alu(0x109, Some(&op.dst), None, Some(&op.src), None);
|
||||
|
||||
let not_mod = matches!(op.src.src_mod, SrcMod::BNot);
|
||||
self.set_field(63..64, not_mod)
|
||||
|
|
@ -1210,10 +1182,10 @@ impl SM70Instr {
|
|||
fn encode_shf(&mut self, op: &OpShf) {
|
||||
self.encode_alu(
|
||||
0x019,
|
||||
Some(op.dst),
|
||||
ALUSrc::from_src(&op.low),
|
||||
ALUSrc::from_src(&op.shift),
|
||||
ALUSrc::from_src(&op.high),
|
||||
Some(&op.dst),
|
||||
Some(&op.low),
|
||||
Some(&op.shift),
|
||||
Some(&op.high),
|
||||
);
|
||||
|
||||
self.set_field(
|
||||
|
|
@ -1234,21 +1206,9 @@ impl SM70Instr {
|
|||
fn encode_f2f(&mut self, op: &OpF2F) {
|
||||
assert!(!op.integer_rnd);
|
||||
if op.src_type.bits() <= 32 && op.dst_type.bits() <= 32 {
|
||||
self.encode_alu(
|
||||
0x104,
|
||||
Some(op.dst),
|
||||
ALUSrc::None,
|
||||
ALUSrc::from_src(&op.src),
|
||||
ALUSrc::None,
|
||||
);
|
||||
self.encode_alu(0x104, Some(&op.dst), None, Some(&op.src), None);
|
||||
} else {
|
||||
self.encode_alu(
|
||||
0x110,
|
||||
Some(op.dst),
|
||||
ALUSrc::None,
|
||||
ALUSrc::from_src(&op.src),
|
||||
ALUSrc::None,
|
||||
);
|
||||
self.encode_alu(0x110, Some(&op.dst), None, Some(&op.src), None);
|
||||
}
|
||||
|
||||
if op.high {
|
||||
|
|
@ -1263,21 +1223,9 @@ impl SM70Instr {
|
|||
|
||||
fn encode_f2i(&mut self, op: &OpF2I) {
|
||||
if op.src_type.bits() <= 32 && op.dst_type.bits() <= 32 {
|
||||
self.encode_alu(
|
||||
0x105,
|
||||
Some(op.dst),
|
||||
ALUSrc::None,
|
||||
ALUSrc::from_src(&op.src),
|
||||
ALUSrc::None,
|
||||
);
|
||||
self.encode_alu(0x105, Some(&op.dst), None, Some(&op.src), None);
|
||||
} else {
|
||||
self.encode_alu(
|
||||
0x111,
|
||||
Some(op.dst),
|
||||
ALUSrc::None,
|
||||
ALUSrc::from_src(&op.src),
|
||||
ALUSrc::None,
|
||||
);
|
||||
self.encode_alu(0x111, Some(&op.dst), None, Some(&op.src), None);
|
||||
}
|
||||
|
||||
self.set_bit(72, op.dst_type.is_signed());
|
||||
|
|
@ -1290,21 +1238,9 @@ impl SM70Instr {
|
|||
|
||||
fn encode_i2f(&mut self, op: &OpI2F) {
|
||||
if op.src_type.bits() <= 32 && op.dst_type.bits() <= 32 {
|
||||
self.encode_alu(
|
||||
0x106,
|
||||
Some(op.dst),
|
||||
ALUSrc::None,
|
||||
ALUSrc::from_src(&op.src),
|
||||
ALUSrc::None,
|
||||
);
|
||||
self.encode_alu(0x106, Some(&op.dst), None, Some(&op.src), None);
|
||||
} else {
|
||||
self.encode_alu(
|
||||
0x112,
|
||||
Some(op.dst),
|
||||
ALUSrc::None,
|
||||
ALUSrc::from_src(&op.src),
|
||||
ALUSrc::None,
|
||||
);
|
||||
self.encode_alu(0x112, Some(&op.dst), None, Some(&op.src), None);
|
||||
}
|
||||
|
||||
self.set_field(60..62, 0_u8); // TODO: subop
|
||||
|
|
@ -1316,21 +1252,9 @@ impl SM70Instr {
|
|||
|
||||
fn encode_frnd(&mut self, op: &OpFRnd) {
|
||||
if op.src_type.bits() <= 32 && op.dst_type.bits() <= 32 {
|
||||
self.encode_alu(
|
||||
0x107,
|
||||
Some(op.dst),
|
||||
ALUSrc::None,
|
||||
ALUSrc::from_src(&op.src),
|
||||
ALUSrc::None,
|
||||
);
|
||||
self.encode_alu(0x107, Some(&op.dst), None, Some(&op.src), None);
|
||||
} else {
|
||||
self.encode_alu(
|
||||
0x113,
|
||||
Some(op.dst),
|
||||
ALUSrc::None,
|
||||
ALUSrc::from_src(&op.src),
|
||||
ALUSrc::None,
|
||||
);
|
||||
self.encode_alu(0x113, Some(&op.dst), None, Some(&op.src), None);
|
||||
}
|
||||
|
||||
self.set_field(84..86, (op.src_type.bits() / 8).ilog2());
|
||||
|
|
@ -1340,23 +1264,17 @@ impl SM70Instr {
|
|||
}
|
||||
|
||||
fn encode_mov(&mut self, op: &OpMov) {
|
||||
self.encode_alu(
|
||||
0x002,
|
||||
Some(op.dst),
|
||||
ALUSrc::None,
|
||||
ALUSrc::from_src(&op.src),
|
||||
ALUSrc::None,
|
||||
);
|
||||
self.encode_alu(0x002, Some(&op.dst), None, Some(&op.src), None);
|
||||
self.set_field(72..76, op.quad_lanes);
|
||||
}
|
||||
|
||||
fn encode_prmt(&mut self, op: &OpPrmt) {
|
||||
self.encode_alu(
|
||||
0x16,
|
||||
Some(op.dst),
|
||||
ALUSrc::from_src(&op.srcs[0]),
|
||||
ALUSrc::from_src(&op.sel),
|
||||
ALUSrc::from_src(&op.srcs[1]),
|
||||
Some(&op.dst),
|
||||
Some(&op.srcs[0]),
|
||||
Some(&op.sel),
|
||||
Some(&op.srcs[1]),
|
||||
);
|
||||
|
||||
self.set_field(
|
||||
|
|
@ -1376,10 +1294,10 @@ impl SM70Instr {
|
|||
fn encode_sel(&mut self, op: &OpSel) {
|
||||
self.encode_alu(
|
||||
0x007,
|
||||
Some(op.dst),
|
||||
ALUSrc::from_src(&op.srcs[0]),
|
||||
ALUSrc::from_src(&op.srcs[1]),
|
||||
ALUSrc::None,
|
||||
Some(&op.dst),
|
||||
Some(&op.srcs[0]),
|
||||
Some(&op.srcs[1]),
|
||||
None,
|
||||
);
|
||||
|
||||
self.set_pred_src(87..90, 90, op.cond);
|
||||
|
|
@ -2223,13 +2141,7 @@ impl SM70Instr {
|
|||
}
|
||||
|
||||
fn encode_warpsync(&mut self, op: &OpWarpSync) {
|
||||
self.encode_alu(
|
||||
0x148,
|
||||
None,
|
||||
ALUSrc::None,
|
||||
ALUSrc::Imm32(op.mask),
|
||||
ALUSrc::None,
|
||||
);
|
||||
self.encode_alu(0x148, None, None, Some(&Src::from(op.mask)), None);
|
||||
self.set_pred_src(87..90, 90, SrcRef::True.into());
|
||||
}
|
||||
|
||||
|
|
@ -2302,10 +2214,10 @@ impl SM70Instr {
|
|||
fn encode_out(&mut self, op: &OpOut) {
|
||||
self.encode_alu(
|
||||
0x124,
|
||||
Some(op.dst),
|
||||
ALUSrc::from_src(&op.handle),
|
||||
ALUSrc::from_src(&op.stream),
|
||||
ALUSrc::None,
|
||||
Some(&op.dst),
|
||||
Some(&op.handle),
|
||||
Some(&op.stream),
|
||||
None,
|
||||
);
|
||||
|
||||
self.set_field(
|
||||
|
|
@ -2321,10 +2233,10 @@ impl SM70Instr {
|
|||
fn encode_out_final(&mut self, op: &OpOutFinal) {
|
||||
self.encode_alu(
|
||||
0x124,
|
||||
Some(Dst::None),
|
||||
ALUSrc::from_src(&op.handle),
|
||||
ALUSrc::from_src(&Src::new_zero()),
|
||||
ALUSrc::None,
|
||||
Some(&Dst::None),
|
||||
Some(&op.handle),
|
||||
Some(&Src::new_zero()),
|
||||
None,
|
||||
);
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue