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radv: allow DGC on the compute queue

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DGC cmdbuf on ACE are executed as IB1 without chaining because IB2
isn't supported on ACE.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24275>
This commit is contained in:
Samuel Pitoiset 2023-06-20 08:40:17 +02:00 • committed by Marge Bot
parent 559da06755
commit 1a90b7a5da
1 changed files with 4 additions and 6 deletions
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10
src/amd/vulkan/radv_cmd_buffer.c
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@ -9470,10 +9470,6 @@ radv_CmdExecuteGeneratedCommandsNV(VkCommandBuffer commandBuffer, VkBool32 isPre
const bool compute = layout->pipeline_bind_point == VK_PIPELINE_BIND_POINT_COMPUTE;
const struct radv_device *device = cmd_buffer->device;
/* The only actions that can be done are draws, so skip on other queues. */
if (cmd_buffer->qf != RADV_QUEUE_GENERAL)
return;
/* Secondary command buffers are needed for the full extension but can't use
* PKT3_INDIRECT_BUFFER.
*/
@ -9505,8 +9501,10 @@ radv_CmdExecuteGeneratedCommandsNV(VkCommandBuffer commandBuffer, VkBool32 isPre
const uint64_t ib_offset = prep_buffer->offset + pGeneratedCommandsInfo->preprocessOffset;
const uint32_t view_mask = cmd_buffer->state.render.view_mask;
radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
radeon_emit(cmd_buffer->cs, 0);
if (!radv_cmd_buffer_uses_mec(cmd_buffer)) {
radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
radeon_emit(cmd_buffer->cs, 0);
}
if (compute || !view_mask) {
device->ws->cs_execute_ib(cmd_buffer->cs, ib_bo, ib_offset, cmdbuf_size >> 2);