From 1a374e1f04c8b9e20478290589effa2823bf5eda Mon Sep 17 00:00:00 2001 From: Lars-Ivar Hesselberg Simonsen Date: Mon, 27 Apr 2026 12:51:06 +0200 Subject: [PATCH] pan/va/ISA: Remove non-existent register_type Register_type does not exist in Valhall and was currently not actually packed. --- src/panfrost/compiler/bifrost/valhall/ISA.xml | 21 ------------------- .../bifrost/valhall/test/assembler-cases.txt | 8 +++---- .../compiler/bifrost/valhall/va_pack.c | 21 ------------------- .../compiler/bifrost/valhall/valhall.py | 1 - 4 files changed, 4 insertions(+), 47 deletions(-) diff --git a/src/panfrost/compiler/bifrost/valhall/ISA.xml b/src/panfrost/compiler/bifrost/valhall/ISA.xml index 92d7ecbdc11..9c412ebf469 100644 --- a/src/panfrost/compiler/bifrost/valhall/ISA.xml +++ b/src/panfrost/compiler/bifrost/valhall/ISA.xml @@ -556,14 +556,6 @@ gather4_a - - Unsized type, part of a register format. - - f - u - s - - Untyped size, part of a register format. 16 @@ -3574,7 +3566,6 @@ Unfiltered textured instruction. - @@ -3601,7 +3592,6 @@ Ordinary texturing instruction using a sampler. - @@ -3630,7 +3620,6 @@ Texture gather instruction. - @@ -3660,7 +3649,6 @@ Texture sample with explicit gradient. - @@ -3687,7 +3675,6 @@ Pair of texture instructions. - @@ -3717,7 +3704,6 @@ - @@ -3742,7 +3728,6 @@ - @@ -3768,7 +3753,6 @@ - @@ -3794,7 +3778,6 @@ - @@ -3819,7 +3802,6 @@ - @@ -3844,7 +3826,6 @@ - @@ -3870,7 +3851,6 @@ - @@ -3896,7 +3876,6 @@ - diff --git a/src/panfrost/compiler/bifrost/valhall/test/assembler-cases.txt b/src/panfrost/compiler/bifrost/valhall/test/assembler-cases.txt index d7eca3c60de..ac40685c05c 100644 --- a/src/panfrost/compiler/bifrost/valhall/test/assembler-cases.txt +++ b/src/panfrost/compiler/bifrost/valhall/test/assembler-cases.txt @@ -213,7 +213,7 @@ c0 00 00 00 00 c9 10 01 IADD_IMM.i32 r9, 0x0, #0x0 f0 00 3c 32 08 40 7f 78 BLEND.slot0.v4.f32.end @r0:r1:r2:r3, blend_descriptor_0.w0, r60, target:0x0 c0 00 00 00 00 f6 10 01 IADD_IMM.i32 r54, 0x0, #0x0 c0 f1 00 00 10 c1 2f 08 BRANCHZI.eq.absolute.wait0 0x0, blend_descriptor_0.w1 -80 00 c0 17 34 7c 25 01 TEX_FETCH.slot0.f.32.2d @r0:r1:r2:r3, @r60:r61, u0 +80 00 c0 13 34 7c 25 01 TEX_FETCH.slot0.32.2d @r0:r1:r2:r3, @r60:r61, u0 80 00 00 00 00 c1 91 02 MOV.i32 r1, u32.w0 81 00 00 00 00 c1 91 02 MOV.i32 r1, u32.w1 8a 00 00 00 00 c1 91 02 MOV.i32 r1, u37.w0 @@ -221,9 +221,9 @@ c0 f1 00 00 10 c1 2f 08 BRANCHZI.eq.absolute.wait0 0x0, blend_descriptor_0.w1 32 00 80 18 02 4c 68 08 ATOM.i32.slot0.aadd.wait0 @r12, [r50:r51], offset:0x0 32 00 00 18 02 8c 69 08 ATOM1_RETURN.i32.slot0.ainc.wait0 @r12, [r50:r51], offset:0x0 32 00 00 18 00 80 69 08 ATOM1_RETURN.i32.slot0.ainc.wait0 @, [r50:r51], offset:0x0 -82 00 80 15 b4 80 38 49 VAR_TEX_SINGLE.slot0.skip.sample_store.f.32.2d.zero.wait @r0:r1:r2:r3, u1, u0.w0 -82 20 80 15 b4 80 38 09 VAR_TEX_SINGLE.slot0.skip.sample_store.f.32.2d.computed.wait0 @r0:r1:r2:r3, u1, u0.w0 -82 20 80 1d 84 80 38 41 VAR_TEX_SINGLE.slot0.skip.sample_store.s.32.2d.computed.wait0126 @r0, u1, u0.w0 +82 00 80 11 b4 80 38 49 VAR_TEX_SINGLE.slot0.skip.sample_store.32.2d.zero.wait @r0:r1:r2:r3, u1, u0.w0 +82 20 80 11 b4 80 38 09 VAR_TEX_SINGLE.slot0.skip.sample_store.32.2d.computed.wait0 @r0:r1:r2:r3, u1, u0.w0 +82 20 80 11 84 80 38 41 VAR_TEX_SINGLE.slot0.skip.sample_store.32.2d.computed.wait0126 @r0, u1, u0.w0 40 c0 c0 80 03 c0 f0 10 ICMP_OR.u32.ne.m1.wait1 r0, r0^, 0x0, 0x0 42 43 40 01 01 c0 f8 00 ICMP_AND.s32.gt.i1 r0, r2^, r3^, r0^ 42 c0 c0 c2 03 c0 f0 10 ICMP_MULTI.u32.ne.u1.wait1 r0, r2^, 0x0, 0x0 diff --git a/src/panfrost/compiler/bifrost/valhall/va_pack.c b/src/panfrost/compiler/bifrost/valhall/va_pack.c index fc7ac40ccb8..d7f42168c7a 100644 --- a/src/panfrost/compiler/bifrost/valhall/va_pack.c +++ b/src/panfrost/compiler/bifrost/valhall/va_pack.c @@ -800,27 +800,6 @@ va_pack_lod_mode(const bi_instr *I) invalid_instruction(I, "LOD mode"); } -static enum va_register_type -va_pack_register_type(const bi_instr *I) -{ - switch (I->register_format) { - case BI_REGISTER_FORMAT_F16: - case BI_REGISTER_FORMAT_F32: - return VA_REGISTER_TYPE_F; - - case BI_REGISTER_FORMAT_U16: - case BI_REGISTER_FORMAT_U32: - return VA_REGISTER_TYPE_U; - - case BI_REGISTER_FORMAT_S16: - case BI_REGISTER_FORMAT_S32: - return VA_REGISTER_TYPE_S; - - default: - invalid_instruction(I, "register type"); - } -} - static enum va_register_format va_pack_register_format(const bi_instr *I) { diff --git a/src/panfrost/compiler/bifrost/valhall/valhall.py b/src/panfrost/compiler/bifrost/valhall/valhall.py index 7bfaa1489d5..7cae9521b87 100644 --- a/src/panfrost/compiler/bifrost/valhall/valhall.py +++ b/src/panfrost/compiler/bifrost/valhall/valhall.py @@ -404,7 +404,6 @@ def valhall_parse_isa(xmlfile): "lod_bias_disable": Modifier("lod_mode", 13, 1), "lod_clamp_disable": Modifier("lod_mode", 14, 1), "write_mask": Modifier("write_mask", 22, 4), - "register_type": Modifier("register_type", 26, 2), "dimension": Modifier("dimension", 28, 2), "skip": Flag("skip", 39), "register_width": Modifier("register_width", 46, 1, force_enum = "register_width"),