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radv: declare streamout SGPRs

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Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Samuel Pitoiset 2018-10-05 17:51:22 +02:00
parent f4fa8de794
commit 19f1b49236
2 changed files with 56 additions and 2 deletions
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55
src/amd/vulkan/radv_nir_to_llvm.c
View file

@ -85,6 +85,12 @@ struct radv_shader_context {
LLVMValueRef persp_sample, persp_center, persp_centroid;
LLVMValueRef linear_sample, linear_center, linear_centroid;
/* Streamout */
LLVMValueRef streamout_buffers;
LLVMValueRef streamout_write_idx;
LLVMValueRef streamout_config;
LLVMValueRef streamout_offset[4];
gl_shader_stage stage;
LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
@ -733,6 +739,12 @@ declare_global_input_sgprs(struct radv_shader_context *ctx,
/* 1 for push constants and dynamic descriptors */
add_array_arg(args, type, &ctx->abi.push_constants);
}
if (ctx->shader_info->info.so.num_outputs) {
add_arg(args, ARG_SGPR,
ac_array_in_const32_addr_space(ctx->ac.v4i32),
&ctx->streamout_buffers);
}
}
static void
@ -774,6 +786,36 @@ declare_vs_input_vgprs(struct radv_shader_context *ctx, struct arg_info *args)
}
}
static void
declare_streamout_sgprs(struct radv_shader_context *ctx, gl_shader_stage stage,
struct arg_info *args)
{
int i;
/* Streamout SGPRs. */
if (ctx->shader_info->info.so.num_outputs) {
assert(stage == MESA_SHADER_VERTEX ||
stage == MESA_SHADER_TESS_EVAL);
if (stage != MESA_SHADER_TESS_EVAL) {
add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->streamout_config);
} else {
args->assign[args->count - 1] = &ctx->streamout_config;
args->types[args->count - 1] = ctx->ac.i32;
}
add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->streamout_write_idx);
}
/* A streamout buffer offset is loaded if the stride is non-zero. */
for (i = 0; i < 4; i++) {
if (!ctx->shader_info->info.so.strides[i])
continue;
add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->streamout_offset[i]);
}
}
static void
declare_tes_input_vgprs(struct radv_shader_context *ctx, struct arg_info *args)
{
@ -825,6 +867,11 @@ set_global_input_locs(struct radv_shader_context *ctx, gl_shader_stage stage,
if (ctx->shader_info->info.loads_push_constants) {
set_loc_shader_ptr(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx);
}
if (ctx->streamout_buffers) {
set_loc_shader_ptr(ctx, AC_UD_STREAMOUT_BUFFERS,
user_sgpr_idx);
}
}
static void
@ -931,9 +978,14 @@ static void create_function(struct radv_shader_context *ctx,
if (needs_view_index)
add_arg(&args, ARG_SGPR, ctx->ac.i32,
&ctx->abi.view_index);
if (ctx->options->key.vs.as_es)
if (ctx->options->key.vs.as_es) {
add_arg(&args, ARG_SGPR, ctx->ac.i32,
&ctx->es2gs_offset);
} else if (ctx->options->key.vs.as_ls) {
/* no extra parameters */
} else {
declare_streamout_sgprs(ctx, stage, &args);
}
declare_vs_input_vgprs(ctx, &args);
break;
@ -1005,6 +1057,7 @@ static void create_function(struct radv_shader_context *ctx,
&ctx->es2gs_offset);
} else {
add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
declare_streamout_sgprs(ctx, stage, &args);
add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
}
declare_tes_input_vgprs(ctx, &args);

3
src/amd/vulkan/radv_shader.h
View file

@ -131,7 +131,8 @@ enum radv_ud_index {
AC_UD_PUSH_CONSTANTS = 1,
AC_UD_INDIRECT_DESCRIPTOR_SETS = 2,
AC_UD_VIEW_INDEX = 3,
AC_UD_SHADER_START = 4,
AC_UD_STREAMOUT_BUFFERS = 4,
AC_UD_SHADER_START = 5,
AC_UD_VS_VERTEX_BUFFERS = AC_UD_SHADER_START,
AC_UD_VS_BASE_VERTEX_START_INSTANCE,
AC_UD_VS_MAX_UD,