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iris: implement gen12 post sync pipe control workaround

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Like Skylake, Gen12 requires a workaround for PIPE_CONTROLs using a
post-sync operation.

v2: Restrict to A0

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3405>
This commit is contained in:
Lionel Landwerlin 2020-01-15 14:06:07 +02:00 • committed by Marge Bot
parent 2c07e03b79
commit 19e7bcee17
1 changed files with 4 additions and 1 deletions
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5
src/gallium/drivers/iris/iris_state.c
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@ -6864,7 +6864,8 @@ iris_emit_raw_pipe_control(struct iris_batch *batch,
imm);
}
if (GEN_GEN == 9 && IS_COMPUTE_PIPELINE(batch) && post_sync_flags) {
if ((GEN_GEN == 9 || (GEN_GEN == 12 && devinfo->revision == 0 /* A0*/)) &&
IS_COMPUTE_PIPELINE(batch) && post_sync_flags) {
/* Project: SKL / Argument: LRI Post Sync Operation [23]
*
* "PIPECONTROL command with “Command Streamer Stall Enable” must be
@ -6873,6 +6874,8 @@ iris_emit_raw_pipe_control(struct iris_batch *batch,
* PIPELINE_SELECT command is set to GPGPU mode of operation)."
*
* The same text exists a few rows below for Post Sync Op.
*
* On Gen12 this is GEN:BUG:1607156449.
*/
iris_emit_raw_pipe_control(batch,
"workaround: CS stall before gpgpu post-sync",