From 19e4dda9a2add2ff98b201cc30993cf61df4ed55 Mon Sep 17 00:00:00 2001 From: Lionel Landwerlin Date: Sat, 5 Apr 2025 23:05:36 +0300 Subject: [PATCH] brw: fix shuffle with scalar/uniform index The fixes commit isn't actually the source of the bug but likely the biggest enabler because it creates scalar values that more easily end up in the shuffle operations. Signed-off-by: Lionel Landwerlin Fixes: 1b24612c57 ("brw/nir: Treat load_*_uniform_block_intel as convergent") Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12927 Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12688 Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12570 Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12905 Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12734 Reviewed-by: Sushma Venkatesh Reddy Reviewed-by: Ian Romanick Part-of: --- src/intel/compiler/brw_generator.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/intel/compiler/brw_generator.cpp b/src/intel/compiler/brw_generator.cpp index a0cbd6afea7..78e667118b0 100644 --- a/src/intel/compiler/brw_generator.cpp +++ b/src/intel/compiler/brw_generator.cpp @@ -379,7 +379,8 @@ brw_generator::generate_shuffle(brw_inst *inst, /* We use VxH indirect addressing, clobbering a0.0 through a0.7. */ struct brw_reg addr = vec8(brw_address_reg(0)); - struct brw_reg group_idx = suboffset(idx, group); + struct brw_reg group_idx = idx.is_scalar || is_uniform(idx) ? + component(idx, 0) : suboffset(idx, group); if (lower_width == 8 && group_idx.width == BRW_WIDTH_16) { /* Things get grumpy if the register is too wide. */