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nvc0/ir: move sample id to second source arg to fix sampler2DMS

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The nvc0 texfetch instruction expects the sample id to be in the second
source (usually used for the offset) rather than as part of the texture
coordinate.

This fixes all the sampler2DMS/Array tests on nvc0.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Christoph Bumiller <e0425955@student.tuwien.ac.at>
Cc: "10.1" <mesa-stable@lists.freedesktop.org>
This commit is contained in:
Ilia Mirkin 2014-03-20 17:37:00 -04:00
parent e5f6b6d0fe
commit 19ba573a57
2 changed files with 12 additions and 4 deletions
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14
src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
View file

@ -666,8 +666,9 @@ NVC0LoweringPass::handleTEX(TexInstruction *i)
const int dim = i->tex.target.getDim() + i->tex.target.isCube();
const int arg = i->tex.target.getArgCount();
const int lyr = arg - (i->tex.target.isMS() ? 2 : 1);
const int chipset = prog->getTarget()->getChipset();
if (prog->getTarget()->getChipset() >= NVISA_GK104_CHIPSET) {
if (chipset >= NVISA_GK104_CHIPSET) {
if (i->tex.rIndirectSrc >= 0 || i->tex.sIndirectSrc >= 0) {
WARN("indirect TEX not implemented\n");
}
@ -697,7 +698,7 @@ NVC0LoweringPass::handleTEX(TexInstruction *i)
}
} else
// (nvc0) generate and move the tsc/tic/array source to the front
if (dim != arg || i->tex.rIndirectSrc >= 0 || i->tex.sIndirectSrc >= 0) {
if (i->tex.target.isArray() || i->tex.rIndirectSrc >= 0 || i->tex.sIndirectSrc >= 0) {
LValue *src = new_LValue(func, FILE_GPR); // 0xttxsaaaa
Value *arrayIndex = i->tex.target.isArray() ? i->getSrc(lyr) : NULL;
@ -728,6 +729,13 @@ NVC0LoweringPass::handleTEX(TexInstruction *i)
i->setSrc(0, src);
}
// For nvc0, the sample id has to be in the second operand, as the offset
// does. Right now we don't know how to pass both in, and this case can't
// happen with OpenGL. On nve0, the sample id is part of the texture
// coordinate argument.
assert(chipset >= NVISA_GK104_CHIPSET ||
!i->tex.useOffsets || !i->tex.target.isMS());
// offset is last source (lod 1st, dc 2nd)
if (i->tex.useOffsets) {
uint32_t value = 0;
@ -741,7 +749,7 @@ NVC0LoweringPass::handleTEX(TexInstruction *i)
i->setSrc(s, bld.loadImm(NULL, value));
}
if (prog->getTarget()->getChipset() >= NVISA_GK104_CHIPSET) {
if (chipset >= NVISA_GK104_CHIPSET) {
//
// If TEX requires more than 4 sources, the 2nd register tuple must be
// aligned to 4, even if it consists of just a single 4-byte register.

2
src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp
View file

@ -1914,7 +1914,7 @@ RegAlloc::InsertConstraintsPass::texConstraintNVC0(TexInstruction *tex)
s = tex->srcCount(0xff);
n = 0;
} else {
s = tex->tex.target.getArgCount();
s = tex->tex.target.getArgCount() - tex->tex.target.isMS();
if (!tex->tex.target.isArray() &&
(tex->tex.rIndirectSrc >= 0 || tex->tex.sIndirectSrc >= 0))
++s;