From 1967b0f0c4d1fc286ea2bf847b69a8f3d2238415 Mon Sep 17 00:00:00 2001 From: Natalie Vock Date: Tue, 18 Feb 2025 16:40:36 +0100 Subject: [PATCH] aco/tests: Add tests for precolored operands in different regs The first test verifies that, if possible, we don't emit unnecessary renames/copies for temporaries where it's possible for them to stay in their current register (if an operand is precolored to the register the temporary is currently residing in). The second test verifies that we correctly choose a non-clobbered operand even if there is one fixed to the temporary's current register. To minimize copies, we'll want to have the live copy of %tmp0 in v[2] there, because v[0-1] gets overwritten. The third test verifies that we add a copy to another free register and rename if all possible precolored operands are clobbered. Part-of: --- src/amd/compiler/tests/test_regalloc.cpp | 49 ++++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/src/amd/compiler/tests/test_regalloc.cpp b/src/amd/compiler/tests/test_regalloc.cpp index 7d3cb60a316..2155fc0f4bc 100644 --- a/src/amd/compiler/tests/test_regalloc.cpp +++ b/src/amd/compiler/tests/test_regalloc.cpp @@ -172,6 +172,55 @@ BEGIN_TEST(regalloc.precolor.different_regs) finish_ra_test(ra_test_policy()); END_TEST +BEGIN_TEST(regalloc.precolor.different_regs_src) + //>> v1: %tmp0:v[0] = p_startpgm + if (!setup_cs("v1", GFX10)) + return; + + //! v1: %tmp1:v[1], v1: %tmp2:v[2] = p_parallelcopy %tmp0:v[0], %tmp0:v[0] + //! p_unit_test %tmp1:v[1], %tmp0:v[0], %tmp2:v[2] + bld.pseudo(aco_opcode::p_unit_test, Operand(inputs[0], PhysReg(256 + 1)), + Operand(inputs[0], PhysReg(256 + 0)), Operand(inputs[0], PhysReg(256 + 2))); + //! p_unit_test %tmp0:v[0] + bld.pseudo(aco_opcode::p_unit_test, Operand(inputs[0])); + + finish_ra_test(ra_test_policy()); +END_TEST + +BEGIN_TEST(regalloc.precolor.different_regs_def_interference) + //>> v1: %tmp0:v[0] = p_startpgm + if (!setup_cs("v1", GFX10)) + return; + + Temp def = bld.tmp(v2); + //! v1: %tmp1:v[1], v1: %tmp2:v[2] = p_parallelcopy %tmp0:v[0], %tmp0:v[0] + //! v2: %tmp3:v[0-1] = p_unit_test %tmp0:v[0], %tmp1:v[1], %tmp2:v[2] + bld.pseudo(aco_opcode::p_unit_test, Definition(def, PhysReg(256 + 0)), + Operand(inputs[0], PhysReg(256 + 0)), Operand(inputs[0], PhysReg(256 + 1)), + Operand(inputs[0], PhysReg(256 + 2))); + //! p_unit_test %tmp2:v[2] + bld.pseudo(aco_opcode::p_unit_test, Operand(inputs[0])); + + finish_ra_test(ra_test_policy()); +END_TEST + +BEGIN_TEST(regalloc.precolor.different_regs_def_all_clobbered) + //>> v1: %tmp0:v[0] = p_startpgm + if (!setup_cs("v1", GFX10)) + return; + + Temp def = bld.tmp(v3); + //! v1: %tmp1:v[1], v1: %tmp2:v[2], v1: %tmp3:v[3] = p_parallelcopy %tmp0:v[0], %tmp0:v[0], %tmp0:v[0] + //! v3: %tmp4:v[0-2] = p_unit_test %tmp0:v[0], %tmp1:v[1], %tmp2:v[2] + bld.pseudo(aco_opcode::p_unit_test, Definition(def, PhysReg(256 + 0)), + Operand(inputs[0], PhysReg(256 + 0)), Operand(inputs[0], PhysReg(256 + 1)), + Operand(inputs[0], PhysReg(256 + 2))); + //! p_unit_test %tmp3:v[3] + bld.pseudo(aco_opcode::p_unit_test, Operand(inputs[0])); + + finish_ra_test(ra_test_policy()); +END_TEST + BEGIN_TEST(regalloc.branch_def_phis_at_merge_block) //>> p_startpgm if (!setup_cs("", GFX10))