From 1943e88d56f6e891dd52c1b46ef6a33a2f4ea172 Mon Sep 17 00:00:00 2001 From: Rhys Perry Date: Fri, 6 Mar 2026 15:17:51 +0000 Subject: [PATCH] radv: move ac_nir_lower_indirect_derefs to end of radv_shader_spirv_to_nir MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Rhys Perry Acked-by: Marek Olšák Reviewed-by: Georg Lehmann Part-of: --- src/amd/vulkan/radv_shader.c | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c index 52343a9c66e..707d167862f 100644 --- a/src/amd/vulkan/radv_shader.c +++ b/src/amd/vulkan/radv_shader.c @@ -853,21 +853,6 @@ radv_shader_spirv_to_nir(const struct radv_compiler_info *compiler_info, struct NIR_PASS(_, nir, radv_nir_lower_primitive_shading_rate, compiler_info->ac->gfx_level); } - /* Indirect lowering must be called after the radv_optimize_nir() loop - * has been called at least once. Otherwise indirect lowering can - * bloat the instruction count of the loop and cause it to be - * considered too large for unrolling. - */ - bool indirect_derefs_lowered = false; - NIR_PASS(indirect_derefs_lowered, nir, ac_nir_lower_indirect_derefs); - NIR_PASS(_, nir, nir_lower_vars_to_ssa); - - if (indirect_derefs_lowered && !stage->key.optimisations_disabled && - nir->info.stage != MESA_SHADER_COMPUTE) { - /* Optimize the lowered code before the linking optimizations. */ - radv_optimize_nir(nir, false); - } - /* Lower immutable/embedded sampler derefs to vec4. */ NIR_PASS(_, nir, radv_nir_lower_immediate_samplers, compiler_info, stage); @@ -892,6 +877,21 @@ radv_shader_spirv_to_nir(const struct radv_compiler_info *compiler_info, struct } } + /* Indirect lowering must be called after the radv_optimize_nir() loop + * has been called at least once. Otherwise indirect lowering can + * bloat the instruction count of the loop and cause it to be + * considered too large for unrolling. + */ + bool indirect_derefs_lowered = false; + NIR_PASS(indirect_derefs_lowered, nir, ac_nir_lower_indirect_derefs); + NIR_PASS(_, nir, nir_lower_vars_to_ssa); + + if (indirect_derefs_lowered && !stage->key.optimisations_disabled && + nir->info.stage != MESA_SHADER_COMPUTE) { + /* Optimize the lowered code before the linking optimizations. */ + radv_optimize_nir(nir, false); + } + return nir; }