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pan: s/NIR_PASS_V/NIR_PASS/
Move away from NIR_PASS_V() like other drivers have done long ago. Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com> Reviewed-by: Chia-I Wu <olvaffe@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32480>
This commit is contained in:
Boris Brezillon
Marge Bot
parent
b47cf63cca
commit
19231c7ae3
5 changed files with 115 additions and 113 deletions
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@ -4798,7 +4798,7 @@ mem_vectorize_cb(unsigned align_mul, unsigned align_offset, unsigned bit_size,
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static void
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bi_optimize_nir(nir_shader *nir, unsigned gpu_id, bool is_blend)
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{
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NIR_PASS_V(nir, nir_opt_shrink_stores, true);
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NIR_PASS(_, nir, nir_opt_shrink_stores, true);
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bool progress;
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@ -4878,9 +4878,9 @@ bi_optimize_nir(nir_shader *nir, unsigned gpu_id, bool is_blend)
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NIR_PASS(progress, nir, nir_opt_dce);
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if (nir->info.stage == MESA_SHADER_FRAGMENT) {
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NIR_PASS_V(nir, nir_shader_intrinsics_pass,
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bifrost_nir_lower_blend_components,
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nir_metadata_control_flow, NULL);
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NIR_PASS(_, nir, nir_shader_intrinsics_pass,
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bifrost_nir_lower_blend_components, nir_metadata_control_flow,
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NULL);
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}
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/* Backend scheduler is purely local, so do some global optimizations
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@ -4889,8 +4889,8 @@ bi_optimize_nir(nir_shader *nir, unsigned gpu_id, bool is_blend)
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nir_move_load_input | nir_move_comparisons |
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nir_move_copies | nir_move_load_ssbo;
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NIR_PASS_V(nir, nir_opt_sink, move_all);
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NIR_PASS_V(nir, nir_opt_move, move_all);
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NIR_PASS(_, nir, nir_opt_sink, move_all);
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NIR_PASS(_, nir, nir_opt_move, move_all);
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/* We might lower attribute, varying, and image indirects. Use the
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* gathered info to skip the extra analysis in the happy path. */
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@ -4901,9 +4901,9 @@ bi_optimize_nir(nir_shader *nir, unsigned gpu_id, bool is_blend)
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nir->info.images_used[0];
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if (any_indirects) {
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NIR_PASS_V(nir, nir_divergence_analysis);
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NIR_PASS_V(nir, bi_lower_divergent_indirects,
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pan_subgroup_size(pan_arch(gpu_id)));
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nir_divergence_analysis(nir);
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NIR_PASS(_, nir, bi_lower_divergent_indirects,
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pan_subgroup_size(pan_arch(gpu_id)));
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}
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}
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@ -5188,11 +5188,11 @@ bifrost_preprocess_nir(nir_shader *nir, unsigned gpu_id)
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* (so we don't accidentally duplicate the epilogue since mesa/st has
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* messed with our I/O quite a bit already) */
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NIR_PASS_V(nir, nir_lower_vars_to_ssa);
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NIR_PASS(_, nir, nir_lower_vars_to_ssa);
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if (nir->info.stage == MESA_SHADER_VERTEX) {
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NIR_PASS_V(nir, nir_lower_viewport_transform);
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NIR_PASS_V(nir, nir_lower_point_size, 1.0, 0.0);
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NIR_PASS(_, nir, nir_lower_viewport_transform);
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NIR_PASS(_, nir, nir_lower_point_size, 1.0, 0.0);
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nir_variable *psiz = nir_find_variable_with_location(
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nir, nir_var_shader_out, VARYING_SLOT_PSIZ);
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@ -5201,7 +5201,7 @@ bifrost_preprocess_nir(nir_shader *nir, unsigned gpu_id)
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}
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/* Get rid of any global vars before we lower to scratch. */
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NIR_PASS_V(nir, nir_lower_global_vars_to_local);
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NIR_PASS(_, nir, nir_lower_global_vars_to_local);
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/* Valhall introduces packed thread local storage, which improves cache
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* locality of TLS access. However, access to packed TLS cannot
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@ -5213,38 +5213,38 @@ bifrost_preprocess_nir(nir_shader *nir, unsigned gpu_id)
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(gpu_id >= 0x9000) ? glsl_get_vec4_size_align_bytes
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: glsl_get_natural_size_align_bytes;
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/* Lower large arrays to scratch and small arrays to bcsel */
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NIR_PASS_V(nir, nir_lower_vars_to_scratch, nir_var_function_temp, 256,
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vars_to_scratch_size_align_func, vars_to_scratch_size_align_func);
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NIR_PASS_V(nir, nir_lower_indirect_derefs, nir_var_function_temp, ~0);
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NIR_PASS(_, nir, nir_lower_vars_to_scratch, nir_var_function_temp, 256,
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vars_to_scratch_size_align_func, vars_to_scratch_size_align_func);
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NIR_PASS(_, nir, nir_lower_indirect_derefs, nir_var_function_temp, ~0);
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NIR_PASS_V(nir, nir_split_var_copies);
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NIR_PASS_V(nir, nir_lower_var_copies);
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NIR_PASS_V(nir, nir_lower_vars_to_ssa);
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NIR_PASS_V(nir, nir_lower_io, nir_var_shader_in | nir_var_shader_out,
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glsl_type_size, nir_lower_io_use_interpolated_input_intrinsics);
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NIR_PASS(_, nir, nir_split_var_copies);
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NIR_PASS(_, nir, nir_lower_var_copies);
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NIR_PASS(_, nir, nir_lower_vars_to_ssa);
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NIR_PASS(_, nir, nir_lower_io, nir_var_shader_in | nir_var_shader_out,
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glsl_type_size, nir_lower_io_use_interpolated_input_intrinsics);
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/* nir_lower[_explicit]_io is lazy and emits mul+add chains even for
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* offsets it could figure out are constant. Do some constant folding
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* before bifrost_nir_lower_store_component below.
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*/
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NIR_PASS_V(nir, nir_opt_constant_folding);
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NIR_PASS(_, nir, nir_opt_constant_folding);
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if (nir->info.stage == MESA_SHADER_FRAGMENT) {
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NIR_PASS_V(nir, nir_lower_mediump_io,
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nir_var_shader_in | nir_var_shader_out,
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~bi_fp32_varying_mask(nir), false);
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NIR_PASS(_, nir, nir_lower_mediump_io,
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nir_var_shader_in | nir_var_shader_out,
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~bi_fp32_varying_mask(nir), false);
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NIR_PASS_V(nir, nir_shader_intrinsics_pass, bi_lower_sample_mask_writes,
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nir_metadata_control_flow, NULL);
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NIR_PASS(_, nir, nir_shader_intrinsics_pass, bi_lower_sample_mask_writes,
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nir_metadata_control_flow, NULL);
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NIR_PASS_V(nir, bifrost_nir_lower_load_output);
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NIR_PASS(_, nir, bifrost_nir_lower_load_output);
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} else if (nir->info.stage == MESA_SHADER_VERTEX) {
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if (gpu_id >= 0x9000) {
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NIR_PASS_V(nir, nir_lower_mediump_io, nir_var_shader_out,
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BITFIELD64_BIT(VARYING_SLOT_PSIZ), false);
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NIR_PASS(_, nir, nir_lower_mediump_io, nir_var_shader_out,
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BITFIELD64_BIT(VARYING_SLOT_PSIZ), false);
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}
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NIR_PASS_V(nir, pan_nir_lower_store_component);
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NIR_PASS(_, nir, pan_nir_lower_store_component);
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}
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nir_lower_mem_access_bit_sizes_options mem_size_options = {
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@ -5254,51 +5254,51 @@ bifrost_preprocess_nir(nir_shader *nir, unsigned gpu_id)
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nir_var_mem_global | nir_var_mem_shared,
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.callback = mem_access_size_align_cb,
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};
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NIR_PASS_V(nir, nir_lower_mem_access_bit_sizes, &mem_size_options);
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NIR_PASS(_, nir, nir_lower_mem_access_bit_sizes, &mem_size_options);
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NIR_PASS_V(nir, nir_shader_intrinsics_pass,
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bi_lower_load_push_const_with_dyn_offset,
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nir_metadata_control_flow, NULL);
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NIR_PASS(_, nir, nir_shader_intrinsics_pass,
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bi_lower_load_push_const_with_dyn_offset, nir_metadata_control_flow,
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NULL);
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nir_lower_ssbo_options ssbo_opts = {
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.native_loads = pan_arch(gpu_id) >= 9,
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.native_offset = pan_arch(gpu_id) >= 9,
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};
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NIR_PASS_V(nir, nir_lower_ssbo, &ssbo_opts);
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NIR_PASS(_, nir, nir_lower_ssbo, &ssbo_opts);
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NIR_PASS_V(nir, pan_lower_sample_pos);
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NIR_PASS_V(nir, nir_lower_bit_size, bi_lower_bit_size, NULL);
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NIR_PASS_V(nir, nir_lower_64bit_phis);
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NIR_PASS_V(nir, pan_lower_helper_invocation);
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NIR_PASS_V(nir, nir_lower_int64);
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NIR_PASS(_, nir, pan_lower_sample_pos);
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NIR_PASS(_, nir, nir_lower_bit_size, bi_lower_bit_size, NULL);
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NIR_PASS(_, nir, nir_lower_64bit_phis);
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NIR_PASS(_, nir, pan_lower_helper_invocation);
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NIR_PASS(_, nir, nir_lower_int64);
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NIR_PASS_V(nir, nir_opt_idiv_const, 8);
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NIR_PASS_V(nir, nir_lower_idiv,
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&(nir_lower_idiv_options){.allow_fp16 = true});
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NIR_PASS(_, nir, nir_opt_idiv_const, 8);
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NIR_PASS(_, nir, nir_lower_idiv,
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&(nir_lower_idiv_options){.allow_fp16 = true});
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NIR_PASS_V(nir, nir_lower_tex,
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&(nir_lower_tex_options){
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.lower_txs_lod = true,
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.lower_txp = ~0,
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.lower_tg4_broadcom_swizzle = true,
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.lower_txd_cube_map = true,
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.lower_invalid_implicit_lod = true,
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.lower_index_to_offset = true,
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});
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NIR_PASS(_, nir, nir_lower_tex,
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&(nir_lower_tex_options){
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.lower_txs_lod = true,
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.lower_txp = ~0,
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.lower_tg4_broadcom_swizzle = true,
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.lower_txd_cube_map = true,
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.lower_invalid_implicit_lod = true,
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.lower_index_to_offset = true,
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});
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NIR_PASS_V(nir, nir_lower_image_atomics_to_global);
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NIR_PASS(_, nir, nir_lower_image_atomics_to_global);
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/* on bifrost, lower MSAA load/stores to 3D load/stores */
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if (pan_arch(gpu_id) < 9)
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NIR_PASS_V(nir, pan_nir_lower_image_ms);
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NIR_PASS(_, nir, pan_nir_lower_image_ms);
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NIR_PASS_V(nir, nir_lower_alu_to_scalar, bi_scalarize_filter, NULL);
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NIR_PASS_V(nir, nir_lower_load_const_to_scalar);
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NIR_PASS_V(nir, nir_lower_phis_to_scalar, true);
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NIR_PASS_V(nir, nir_lower_flrp, 16 | 32 | 64, false /* always_precise */);
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NIR_PASS_V(nir, nir_lower_var_copies);
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NIR_PASS_V(nir, nir_lower_alu);
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NIR_PASS_V(nir, nir_lower_frag_coord_to_pixel_coord);
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NIR_PASS(_, nir, nir_lower_alu_to_scalar, bi_scalarize_filter, NULL);
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NIR_PASS(_, nir, nir_lower_load_const_to_scalar);
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NIR_PASS(_, nir, nir_lower_phis_to_scalar, true);
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NIR_PASS(_, nir, nir_lower_flrp, 16 | 32 | 64, false /* always_precise */);
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NIR_PASS(_, nir, nir_lower_var_copies);
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NIR_PASS(_, nir, nir_lower_alu);
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NIR_PASS(_, nir, nir_lower_frag_coord_to_pixel_coord);
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}
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static bi_context *
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@ -5329,8 +5329,8 @@ bi_compile_variant_nir(nir_shader *nir,
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if (offset == 0)
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ctx->nir = nir = nir_shader_clone(ctx, nir);
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NIR_PASS_V(nir, nir_shader_instructions_pass, bifrost_nir_specialize_idvs,
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nir_metadata_control_flow, &idvs);
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NIR_PASS(_, nir, nir_shader_instructions_pass,
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bifrost_nir_specialize_idvs, nir_metadata_control_flow, &idvs);
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/* After specializing, clean up the mess */
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bool progress = true;
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@ -5687,7 +5687,7 @@ bifrost_compile_shader_nir(nir_shader *nir,
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/* Combine stores late, to give the driver a chance to lower dual-source
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* blending as regular store_output intrinsics.
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*/
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NIR_PASS_V(nir, pan_nir_lower_zs_store);
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NIR_PASS(_, nir, pan_nir_lower_zs_store);
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bi_optimize_nir(nir, inputs->gpu_id, inputs->is_blend);
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@ -713,7 +713,7 @@ GENX(pan_blend_create_shader)(const struct pan_blend_state *state,
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b.shader->info.io_lowered = true;
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NIR_PASS_V(b.shader, nir_lower_blend, &options);
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NIR_PASS(_, b.shader, nir_lower_blend, &options);
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return b.shader;
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}
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@ -884,11 +884,11 @@ GENX(pan_blend_get_shader_locked)(struct pan_blend_shader_cache *cache,
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pan_shader_preprocess(nir, inputs.gpu_id);
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#if PAN_ARCH >= 6
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NIR_PASS_V(nir, GENX(pan_inline_rt_conversion), rt_formats);
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NIR_PASS(_, nir, GENX(pan_inline_rt_conversion), rt_formats);
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#else
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NIR_PASS_V(nir, pan_lower_framebuffer, rt_formats,
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pan_raw_format_mask_midgard(rt_formats), MAX2(key.nr_samples, 1),
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cache->gpu_id < 0x700);
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NIR_PASS(_, nir, pan_lower_framebuffer, rt_formats,
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pan_raw_format_mask_midgard(rt_formats), MAX2(key.nr_samples, 1),
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cache->gpu_id < 0x700);
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#endif
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GENX(pan_shader_compile)(nir, &inputs, &variant->binary, &info);
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@ -393,31 +393,31 @@ midgard_preprocess_nir(nir_shader *nir, unsigned gpu_id)
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* (so we don't accidentally duplicate the epilogue since mesa/st has
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* messed with our I/O quite a bit already).
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*/
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NIR_PASS_V(nir, nir_lower_vars_to_ssa);
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NIR_PASS(_, nir, nir_lower_vars_to_ssa);
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if (nir->info.stage == MESA_SHADER_VERTEX) {
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NIR_PASS_V(nir, nir_lower_viewport_transform);
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NIR_PASS_V(nir, nir_lower_point_size, 1.0, 0.0);
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NIR_PASS(_, nir, nir_lower_viewport_transform);
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NIR_PASS(_, nir, nir_lower_point_size, 1.0, 0.0);
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}
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NIR_PASS_V(nir, nir_lower_var_copies);
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NIR_PASS_V(nir, nir_lower_vars_to_ssa);
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NIR_PASS_V(nir, nir_split_var_copies);
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NIR_PASS_V(nir, nir_lower_var_copies);
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NIR_PASS_V(nir, nir_lower_global_vars_to_local);
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NIR_PASS_V(nir, nir_lower_var_copies);
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NIR_PASS_V(nir, nir_lower_vars_to_ssa);
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NIR_PASS(_, nir, nir_lower_var_copies);
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NIR_PASS(_, nir, nir_lower_vars_to_ssa);
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NIR_PASS(_, nir, nir_split_var_copies);
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NIR_PASS(_, nir, nir_lower_var_copies);
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NIR_PASS(_, nir, nir_lower_global_vars_to_local);
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NIR_PASS(_, nir, nir_lower_var_copies);
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NIR_PASS(_, nir, nir_lower_vars_to_ssa);
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NIR_PASS_V(nir, nir_lower_io, nir_var_shader_in | nir_var_shader_out,
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glsl_type_size, nir_lower_io_use_interpolated_input_intrinsics);
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NIR_PASS(_, nir, nir_lower_io, nir_var_shader_in | nir_var_shader_out,
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glsl_type_size, nir_lower_io_use_interpolated_input_intrinsics);
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if (nir->info.stage == MESA_SHADER_VERTEX) {
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/* nir_lower[_explicit]_io is lazy and emits mul+add chains even
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* for offsets it could figure out are constant. Do some
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* constant folding before pan_nir_lower_store_component below.
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*/
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NIR_PASS_V(nir, nir_opt_constant_folding);
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NIR_PASS_V(nir, pan_nir_lower_store_component);
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NIR_PASS(_, nir, nir_opt_constant_folding);
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NIR_PASS(_, nir, pan_nir_lower_store_component);
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}
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/* Could be eventually useful for Vulkan, but we don't expect it to have
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@ -431,22 +431,22 @@ midgard_preprocess_nir(nir_shader *nir, unsigned gpu_id)
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.callback = mem_access_size_align_cb,
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};
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NIR_PASS_V(nir, nir_lower_mem_access_bit_sizes, &mem_size_options);
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NIR_PASS_V(nir, nir_lower_alu_width, lower_vec816_alu, NULL);
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NIR_PASS_V(nir, nir_lower_alu_vec8_16_srcs);
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NIR_PASS(_, nir, nir_lower_mem_access_bit_sizes, &mem_size_options);
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NIR_PASS(_, nir, nir_lower_alu_width, lower_vec816_alu, NULL);
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NIR_PASS(_, nir, nir_lower_alu_vec8_16_srcs);
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}
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NIR_PASS_V(nir, nir_lower_ssbo, NULL);
|
||||
NIR_PASS_V(nir, pan_nir_lower_zs_store);
|
||||
NIR_PASS(_, nir, nir_lower_ssbo, NULL);
|
||||
NIR_PASS(_, nir, pan_nir_lower_zs_store);
|
||||
|
||||
NIR_PASS_V(nir, nir_lower_frexp);
|
||||
NIR_PASS_V(nir, midgard_nir_lower_global_load);
|
||||
NIR_PASS(_, nir, nir_lower_frexp);
|
||||
NIR_PASS(_, nir, midgard_nir_lower_global_load);
|
||||
|
||||
nir_lower_idiv_options idiv_options = {
|
||||
.allow_fp16 = true,
|
||||
};
|
||||
|
||||
NIR_PASS_V(nir, nir_lower_idiv, &idiv_options);
|
||||
NIR_PASS(_, nir, nir_lower_idiv, &idiv_options);
|
||||
|
||||
nir_lower_tex_options lower_tex_options = {
|
||||
.lower_txs_lod = true,
|
||||
|
|
@ -456,30 +456,30 @@ midgard_preprocess_nir(nir_shader *nir, unsigned gpu_id)
|
|||
.lower_invalid_implicit_lod = true,
|
||||
};
|
||||
|
||||
NIR_PASS_V(nir, nir_lower_tex, &lower_tex_options);
|
||||
NIR_PASS_V(nir, nir_lower_image_atomics_to_global);
|
||||
NIR_PASS(_, nir, nir_lower_tex, &lower_tex_options);
|
||||
NIR_PASS(_, nir, nir_lower_image_atomics_to_global);
|
||||
|
||||
/* TEX_GRAD fails to apply sampler descriptor settings on some
|
||||
* implementations, requiring a lowering.
|
||||
*/
|
||||
if (quirks & MIDGARD_BROKEN_LOD)
|
||||
NIR_PASS_V(nir, midgard_nir_lod_errata);
|
||||
NIR_PASS(_, nir, midgard_nir_lod_errata);
|
||||
|
||||
/* lower MSAA image operations to 3D load before coordinate lowering */
|
||||
NIR_PASS_V(nir, pan_nir_lower_image_ms);
|
||||
NIR_PASS(_, nir, pan_nir_lower_image_ms);
|
||||
|
||||
/* Midgard image ops coordinates are 16-bit instead of 32-bit */
|
||||
NIR_PASS_V(nir, midgard_nir_lower_image_bitsize);
|
||||
NIR_PASS(_, nir, midgard_nir_lower_image_bitsize);
|
||||
|
||||
if (nir->info.stage == MESA_SHADER_FRAGMENT)
|
||||
NIR_PASS_V(nir, nir_lower_helper_writes, true);
|
||||
NIR_PASS(_, nir, nir_lower_helper_writes, true);
|
||||
|
||||
NIR_PASS_V(nir, pan_lower_helper_invocation);
|
||||
NIR_PASS_V(nir, pan_lower_sample_pos);
|
||||
NIR_PASS_V(nir, midgard_nir_lower_algebraic_early);
|
||||
NIR_PASS_V(nir, nir_lower_alu_to_scalar, mdg_should_scalarize, NULL);
|
||||
NIR_PASS_V(nir, nir_lower_flrp, 16 | 32 | 64, false /* always_precise */);
|
||||
NIR_PASS_V(nir, nir_lower_var_copies);
|
||||
NIR_PASS(_, nir, pan_lower_helper_invocation);
|
||||
NIR_PASS(_, nir, pan_lower_sample_pos);
|
||||
NIR_PASS(_, nir, midgard_nir_lower_algebraic_early);
|
||||
NIR_PASS(_, nir, nir_lower_alu_to_scalar, mdg_should_scalarize, NULL);
|
||||
NIR_PASS(_, nir, nir_lower_flrp, 16 | 32 | 64, false /* always_precise */);
|
||||
NIR_PASS(_, nir, nir_lower_var_copies);
|
||||
}
|
||||
|
||||
static void
|
||||
|
|
@ -509,7 +509,7 @@ optimise_nir(nir_shader *nir, unsigned quirks, bool is_blend)
|
|||
NULL);
|
||||
} while (progress);
|
||||
|
||||
NIR_PASS_V(nir, nir_lower_alu_to_scalar, mdg_should_scalarize, NULL);
|
||||
NIR_PASS(_, nir, nir_lower_alu_to_scalar, mdg_should_scalarize, NULL);
|
||||
|
||||
/* Run after opts so it can hit more */
|
||||
if (!is_blend)
|
||||
|
|
@ -533,7 +533,7 @@ optimise_nir(nir_shader *nir, unsigned quirks, bool is_blend)
|
|||
/* Now that booleans are lowered, we can run out late opts */
|
||||
NIR_PASS(progress, nir, midgard_nir_lower_algebraic_late);
|
||||
NIR_PASS(progress, nir, midgard_nir_cancel_inot);
|
||||
NIR_PASS_V(nir, midgard_nir_type_csel);
|
||||
NIR_PASS(_, nir, midgard_nir_type_csel);
|
||||
|
||||
/* Clean up after late opts */
|
||||
do {
|
||||
|
|
@ -550,8 +550,8 @@ optimise_nir(nir_shader *nir, unsigned quirks, bool is_blend)
|
|||
nir_move_load_input | nir_move_comparisons |
|
||||
nir_move_copies | nir_move_load_ssbo;
|
||||
|
||||
NIR_PASS_V(nir, nir_opt_sink, move_all);
|
||||
NIR_PASS_V(nir, nir_opt_move, move_all);
|
||||
NIR_PASS(_, nir, nir_opt_sink, move_all);
|
||||
NIR_PASS(_, nir, nir_opt_move, move_all);
|
||||
|
||||
/* Take us out of SSA */
|
||||
NIR_PASS(progress, nir, nir_convert_from_ssa, true);
|
||||
|
|
@ -561,7 +561,7 @@ optimise_nir(nir_shader *nir, unsigned quirks, bool is_blend)
|
|||
NIR_PASS(progress, nir, nir_lower_vec_to_regs, NULL, NULL);
|
||||
|
||||
NIR_PASS(progress, nir, nir_opt_dce);
|
||||
NIR_PASS_V(nir, nir_trivialize_registers);
|
||||
nir_trivialize_registers(nir);
|
||||
}
|
||||
|
||||
/* Do not actually emit a load; instead, cache the constant for inlining */
|
||||
|
|
|
|||
|
|
@ -4,5 +4,5 @@
|
|||
bool midgard_nir_lower_algebraic_early(nir_shader *shader);
|
||||
bool midgard_nir_lower_algebraic_late(nir_shader *shader);
|
||||
bool midgard_nir_cancel_inot(nir_shader *shader);
|
||||
void midgard_nir_type_csel(nir_shader *shader);
|
||||
bool midgard_nir_type_csel(nir_shader *shader);
|
||||
bool midgard_nir_lower_image_bitsize(nir_shader *shader);
|
||||
|
|
|
|||
|
|
@ -23,7 +23,7 @@ pass(nir_builder *b, nir_alu_instr *alu, void *data)
|
|||
}
|
||||
}
|
||||
|
||||
void
|
||||
bool
|
||||
midgard_nir_type_csel(nir_shader *shader)
|
||||
{
|
||||
nir_function_impl *impl = nir_shader_get_entrypoint(shader);
|
||||
|
|
@ -33,8 +33,10 @@ midgard_nir_type_csel(nir_shader *shader)
|
|||
calloc(BITSET_WORDS(impl->ssa_alloc), sizeof(BITSET_WORD));
|
||||
nir_gather_types(impl, float_types, NULL);
|
||||
|
||||
nir_shader_alu_pass(shader, pass, nir_metadata_control_flow,
|
||||
float_types);
|
||||
bool progress =
|
||||
nir_shader_alu_pass(shader, pass, nir_metadata_control_flow, float_types);
|
||||
|
||||
free(float_types);
|
||||
|
||||
return progress;
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue