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aco/ra: make use of Precolored flag
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31387>
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1 changed files with 6 additions and 8 deletions
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@ -799,7 +799,6 @@ adjust_max_used_regs(ra_ctx& ctx, RegClass rc, unsigned reg)
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enum UpdateRenames {
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rename_not_killed_ops = 0x1,
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rename_precolored_ops = 0x4,
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};
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MESA_DEFINE_CPP_ENUM_BITFIELD_OPERATORS(UpdateRenames);
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@ -880,8 +879,7 @@ update_renames(ra_ctx& ctx, RegisterFile& reg_file,
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continue;
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if (op.tempId() == copy.first.tempId()) {
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/* only rename precolored operands if the copy-location matches */
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bool omit_renaming = (flags & rename_precolored_ops) && op.isFixed() &&
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op.physReg() != copy.second.physReg();
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bool omit_renaming = op.isPrecolored() && op.physReg() != copy.second.physReg();
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/* Omit renaming in some cases for p_create_vector in order to avoid
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* unnecessary shuffle code. */
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@ -908,7 +906,7 @@ update_renames(ra_ctx& ctx, RegisterFile& reg_file,
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op.setTemp(copy.second.getTemp());
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op.setFixed(copy.second.physReg());
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fill = !op.isKillBeforeDef() || (flags & rename_precolored_ops);
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fill = !op.isKillBeforeDef() || op.isPrecolored();
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}
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}
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@ -2097,9 +2095,10 @@ handle_fixed_operands(ra_ctx& ctx, RegisterFile& register_file,
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for (unsigned i = 0; i < instr->operands.size(); i++) {
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Operand& op = instr->operands[i];
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if (!op.isTemp() || !op.isFixed())
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if (!op.isPrecolored())
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continue;
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assert(op.isTemp());
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PhysReg src = ctx.assignments[op.tempId()].reg;
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adjust_max_used_regs(ctx, op.regClass(), op.physReg());
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@ -2139,8 +2138,7 @@ handle_fixed_operands(ra_ctx& ctx, RegisterFile& register_file,
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}
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get_regs_for_copies(ctx, tmp_file, parallelcopy, blocking_vars, instr, PhysRegInterval());
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update_renames(ctx, register_file, parallelcopy, instr,
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rename_not_killed_ops | rename_precolored_ops);
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update_renames(ctx, register_file, parallelcopy, instr, rename_not_killed_ops);
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}
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void
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@ -3086,7 +3084,7 @@ register_allocation(Program* program, ra_test_policy policy)
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assert(ctx.assignments[operand.tempId()].assigned);
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fixed |=
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operand.isFixed() && ctx.assignments[operand.tempId()].reg != operand.physReg();
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operand.isPrecolored() && ctx.assignments[operand.tempId()].reg != operand.physReg();
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}
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bool is_writelane = instr->opcode == aco_opcode::v_writelane_b32 ||
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