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tu: Do not flush ccu in clear/blits during renderpass

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For clear/blits ccu flush not only worse for perf, but also messes up
flush_bits when executed in a conditional set of commands.

We already don't flush for 3d blits.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6419

Fixes: 487aa807bd
("tu: Rewrite flushing to use barriers")

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16352>
This commit is contained in:
Danylo Piliaiev 2022-05-05 20:29:05 +03:00 • committed by Marge Bot
parent 66888d5121
commit 187d3df52c
2 changed files with 5 additions and 1 deletions
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4
src/freedreno/vulkan/tu_clear_blit.c
View file

@ -333,7 +333,9 @@ r2d_setup(struct tu_cmd_buffer *cmd,
{
assert(samples == VK_SAMPLE_COUNT_1_BIT);
tu_emit_cache_flush_ccu(cmd, cs, TU_CMD_CCU_SYSMEM);
if (!cmd->state.pass) {
tu_emit_cache_flush_ccu(cmd, cs, TU_CMD_CCU_SYSMEM);
}
r2d_setup_common(cmd, cs, format, aspect_mask, blit_param, clear, ubwc, false);
}

2
src/freedreno/vulkan/tu_cmd_buffer.c
View file

@ -159,6 +159,8 @@ tu_emit_cache_flush_ccu(struct tu_cmd_buffer *cmd_buffer,
enum tu_cmd_flush_bits flushes = cmd_buffer->state.cache.flush_bits;
assert(ccu_state != TU_CMD_CCU_UNKNOWN);
/* It's unsafe to flush inside condition because we clear flush_bits */
assert(!cs->cond_flags);
/* Changing CCU state must involve invalidating the CCU. In sysmem mode,
* the CCU may also contain data that we haven't flushed out yet, so we