fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-06-13 05:08:20 +02:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

tu: Use fdl6_view in tu_image_view and cross-check

Browse source 
Because some of the fields aren't filled out when a format doesn't
support rendering, we temporarily clear the structure so that we can
compare.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13359>
This commit is contained in:
Connor Abbott 2021-10-13 17:51:13 +02:00 • committed by Marge Bot
parent 5509132a80
commit 1874e12f19
7 changed files with 181 additions and 119 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

1
src/freedreno/fdl/fd6_view.c
View file

@ -108,6 +108,7 @@ void
fdl6_view_init(struct fdl6_view *view, const struct fdl_layout **layouts,
const struct fdl_view_args *args, bool has_z24uint_s8uint)
{
memset(view, 0, sizeof(*view));
const struct fdl_layout *layout = layouts[0];
uint32_t width = u_minify(layout->width0, args->base_miplevel);
uint32_t height = u_minify(layout->height0, args->base_miplevel);

34
src/freedreno/vulkan/tu_clear_blit.c
View file

@ -148,13 +148,13 @@ r2d_src(struct tu_cmd_buffer *cmd,
uint32_t layer,
VkFilter filter)
{
uint32_t src_info = iview->SP_PS_2D_SRC_INFO;
uint32_t src_info = iview->view.SP_PS_2D_SRC_INFO;
if (filter != VK_FILTER_NEAREST)
src_info |= A6XX_SP_PS_2D_SRC_INFO_FILTER;
tu_cs_emit_pkt4(cs, REG_A6XX_SP_PS_2D_SRC_INFO, 5);
tu_cs_emit(cs, src_info);
tu_cs_emit(cs, iview->SP_PS_2D_SRC_SIZE);
tu_cs_emit(cs, iview->view.SP_PS_2D_SRC_SIZE);
tu_cs_image_ref_2d(cs, iview, layer, true);
tu_cs_emit_pkt4(cs, REG_A6XX_SP_PS_2D_SRC_FLAGS, 3);
@ -170,7 +170,7 @@ r2d_src_stencil(struct tu_cmd_buffer *cmd,
{
tu_cs_emit_pkt4(cs, REG_A6XX_SP_PS_2D_SRC_INFO, 5);
tu_cs_emit(cs, tu_image_view_stencil(iview, SP_PS_2D_SRC_INFO) & ~A6XX_SP_PS_2D_SRC_INFO_FLAGS);
tu_cs_emit(cs, iview->SP_PS_2D_SRC_SIZE);
tu_cs_emit(cs, iview->view.SP_PS_2D_SRC_SIZE);
tu_cs_emit_qw(cs, iview->stencil_base_addr + iview->stencil_layer_size * layer);
/* SP_PS_2D_SRC_PITCH has shifted pitch field */
tu_cs_emit(cs, iview->stencil_PITCH << 9);
@ -201,7 +201,7 @@ static void
r2d_dst(struct tu_cs *cs, const struct tu_image_view *iview, uint32_t layer)
{
tu_cs_emit_pkt4(cs, REG_A6XX_RB_2D_DST_INFO, 4);
tu_cs_emit(cs, iview->RB_2D_DST_INFO);
tu_cs_emit(cs, iview->view.RB_2D_DST_INFO);
tu_cs_image_ref_2d(cs, iview, layer, false);
tu_cs_emit_pkt4(cs, REG_A6XX_RB_2D_DST_FLAGS, 3);
@ -858,9 +858,9 @@ r3d_src(struct tu_cmd_buffer *cmd,
uint32_t layer,
VkFilter filter)
{
r3d_src_common(cmd, cs, iview->descriptor,
iview->layer_size * layer,
iview->ubwc_layer_size * layer,
r3d_src_common(cmd, cs, iview->view.descriptor,
iview->view.layer_size * layer,
iview->view.ubwc_layer_size * layer,
filter);
}
@ -906,7 +906,7 @@ r3d_src_gmem(struct tu_cmd_buffer *cmd,
uint32_t cpp)
{
uint32_t desc[A6XX_TEX_CONST_DWORDS];
memcpy(desc, iview->descriptor, sizeof(desc));
memcpy(desc, iview->view.descriptor, sizeof(desc));
/* patch the format so that depth/stencil get the right format */
desc[0] &= ~A6XX_TEX_CONST_0_FMT__MASK;
@ -931,14 +931,14 @@ static void
r3d_dst(struct tu_cs *cs, const struct tu_image_view *iview, uint32_t layer)
{
tu_cs_emit_pkt4(cs, REG_A6XX_RB_MRT_BUF_INFO(0), 6);
tu_cs_emit(cs, iview->RB_MRT_BUF_INFO);
tu_cs_emit(cs, iview->view.RB_MRT_BUF_INFO);
tu_cs_image_ref(cs, iview, layer);
tu_cs_emit(cs, 0);
tu_cs_emit_pkt4(cs, REG_A6XX_RB_MRT_FLAG_BUFFER(0), 3);
tu_cs_image_flag_ref(cs, iview, layer);
tu_cs_emit_regs(cs, A6XX_RB_RENDER_CNTL(.flag_mrts = iview->ubwc_enabled));
tu_cs_emit_regs(cs, A6XX_RB_RENDER_CNTL(.flag_mrts = iview->view.ubwc_enabled));
}
static void
@ -2047,7 +2047,7 @@ resolve_sysmem(struct tu_cmd_buffer *cmd,
trace_start_sysmem_resolve(&cmd->trace, cs);
ops->setup(cmd, cs, format, VK_IMAGE_ASPECT_COLOR_BIT,
0, false, dst->ubwc_enabled, VK_SAMPLE_COUNT_1_BIT);
0, false, dst->view.ubwc_enabled, VK_SAMPLE_COUNT_1_BIT);
ops->coords(cs, &rect->offset, &rect->offset, &rect->extent);
for_each_layer(i, layer_mask, layers) {
@ -2569,7 +2569,7 @@ clear_sysmem_attachment(struct tu_cmd_buffer *cmd,
trace_start_sysmem_clear(&cmd->trace, cs);
ops->setup(cmd, cs, format, clear_mask, 0, true, iview->ubwc_enabled,
ops->setup(cmd, cs, format, clear_mask, 0, true, iview->view.ubwc_enabled,
cmd->state.pass->attachments[a].samples);
ops->coords(cs, &info->renderArea.offset, NULL, &info->renderArea.extent);
ops->clear_value(cs, format, &info->pClearValues[a]);
@ -2684,7 +2684,7 @@ tu_emit_blit(struct tu_cmd_buffer *cmd,
tu_cs_emit_regs(cs,
A6XX_RB_BLIT_BASE_GMEM(attachment->gmem_offset_stencil));
} else {
tu_cs_emit(cs, iview->RB_BLIT_DST_INFO);
tu_cs_emit(cs, iview->view.RB_BLIT_DST_INFO);
tu_cs_image_ref_2d(cs, iview, 0, false);
tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_FLAG_DST, 3);
@ -2764,7 +2764,7 @@ store_cp_blit(struct tu_cmd_buffer *cmd,
uint32_t cpp)
{
r2d_setup_common(cmd, cs, format, VK_IMAGE_ASPECT_COLOR_BIT, 0, false,
iview->ubwc_enabled, true);
iview->view.ubwc_enabled, true);
if (separate_stencil)
r2d_dst_stencil(cs, iview, 0);
else
@ -2813,7 +2813,7 @@ store_3d_blit(struct tu_cmd_buffer *cmd,
uint32_t cpp)
{
r3d_setup(cmd, cs, format, VK_IMAGE_ASPECT_COLOR_BIT, 0, false,
iview->ubwc_enabled, dst_samples);
iview->view.ubwc_enabled, dst_samples);
r3d_coords(cs, &render_area->offset, &render_area->offset, &render_area->extent);
@ -2862,11 +2862,11 @@ tu_store_gmem_attachment(struct tu_cmd_buffer *cmd,
* required y padding in the layout (except for the last level)
*/
bool need_y2_align =
y2 != iview->extent.height || iview->need_y2_align;
y2 != iview->view.height || iview->view.need_y2_align;
bool unaligned =
x1 % phys_dev->info->gmem_align_w ||
(x2 % phys_dev->info->gmem_align_w && x2 != iview->extent.width) ||
(x2 % phys_dev->info->gmem_align_w && x2 != iview->view.width) ||
y1 % phys_dev->info->gmem_align_h || (y2 % phys_dev->info->gmem_align_h && need_y2_align);
/* D32_SFLOAT_S8_UINT is quite special format: it has two planes,

10
src/freedreno/vulkan/tu_cmd_buffer.c
View file

@ -263,12 +263,12 @@ tu6_emit_mrt(struct tu_cmd_buffer *cmd,
const struct tu_image_view *iview = cmd->state.attachments[a];
tu_cs_emit_pkt4(cs, REG_A6XX_RB_MRT_BUF_INFO(i), 6);
tu_cs_emit(cs, iview->RB_MRT_BUF_INFO);
tu_cs_emit(cs, iview->view.RB_MRT_BUF_INFO);
tu_cs_image_ref(cs, iview, 0);
tu_cs_emit(cs, cmd->state.pass->attachments[a].gmem_offset);
tu_cs_emit_regs(cs,
A6XX_SP_FS_MRT_REG(i, .dword = iview->SP_FS_MRT_REG));
A6XX_SP_FS_MRT_REG(i, .dword = iview->view.SP_FS_MRT_REG));
tu_cs_emit_pkt4(cs, REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR(i), 3);
tu_cs_image_flag_ref(cs, iview, 0);
@ -371,7 +371,7 @@ tu6_emit_render_cntl(struct tu_cmd_buffer *cmd,
continue;
const struct tu_image_view *iview = cmd->state.attachments[a];
if (iview->ubwc_enabled)
if (iview->view.ubwc_enabled)
mrts_ubwc_enable |= 1 << i;
}
@ -380,7 +380,7 @@ tu6_emit_render_cntl(struct tu_cmd_buffer *cmd,
const uint32_t a = subpass->depth_stencil_attachment.attachment;
if (a != VK_ATTACHMENT_UNUSED) {
const struct tu_image_view *iview = cmd->state.attachments[a];
if (iview->ubwc_enabled)
if (iview->view.ubwc_enabled)
cntl |= A6XX_RB_RENDER_CNTL_FLAG_DEPTH;
}
@ -1073,7 +1073,7 @@ tu_emit_input_attachments(struct tu_cmd_buffer *cmd,
uint32_t gmem_offset = att->gmem_offset;
uint32_t cpp = att->cpp;
memcpy(dst, iview->descriptor, A6XX_TEX_CONST_DWORDS * 4);
memcpy(dst, iview->view.descriptor, A6XX_TEX_CONST_DWORDS * 4);
if (i % 2 == 1 && att->format == VK_FORMAT_D24_UNORM_S8_UINT) {
/* note this works because spec says fb and input attachments

4
src/freedreno/vulkan/tu_descriptor_set.c
View file

@ -875,9 +875,9 @@ write_image_descriptor(uint32_t *dst,
TU_FROM_HANDLE(tu_image_view, iview, image_info->imageView);
if (descriptor_type == VK_DESCRIPTOR_TYPE_STORAGE_IMAGE) {
memcpy(dst, iview->storage_descriptor, sizeof(iview->storage_descriptor));
memcpy(dst, iview->view.storage_descriptor, sizeof(iview->view.storage_descriptor));
} else {
memcpy(dst, iview->descriptor, sizeof(iview->descriptor));
memcpy(dst, iview->view.descriptor, sizeof(iview->view.descriptor));
}
}

2
src/freedreno/vulkan/tu_formats.c
View file

@ -60,7 +60,7 @@ tu6_format_vtx_supported(VkFormat vk_format)
* for VK RGB formats yet, and we'd have to switch all consumers of that
* function at once.
*/
static enum pipe_format
enum pipe_format
tu_vk_format_to_pipe_format(VkFormat vk_format)
{
switch (vk_format) {

213
src/freedreno/vulkan/tu_image.c
View file

@ -82,6 +82,30 @@ tu6_plane_index(VkFormat format, VkImageAspectFlags aspect_mask)
}
}
static enum pipe_format
tu_format_for_aspect(enum pipe_format format, VkImageAspectFlags aspect_mask)
{
switch (format) {
case PIPE_FORMAT_Z24_UNORM_S8_UINT:
if (aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT)
return PIPE_FORMAT_Z24_UNORM_S8_UINT_AS_R8G8B8A8;
if (aspect_mask & VK_IMAGE_ASPECT_STENCIL_BIT) {
if (aspect_mask & VK_IMAGE_ASPECT_DEPTH_BIT)
return PIPE_FORMAT_Z24_UNORM_S8_UINT;
else
return PIPE_FORMAT_X24S8_UINT;
} else {
return PIPE_FORMAT_Z24X8_UNORM;
}
case PIPE_FORMAT_Z24X8_UNORM:
if (aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT)
return PIPE_FORMAT_Z24_UNORM_S8_UINT_AS_R8G8B8A8;
return PIPE_FORMAT_Z24X8_UNORM;
default:
return format;
}
}
static void
compose_swizzle(unsigned char *swiz, const VkComponentMapping *mapping)
{
@ -170,9 +194,9 @@ tu6_texswiz(const VkComponentMapping *comps,
void
tu_cs_image_ref(struct tu_cs *cs, const struct tu_image_view *iview, uint32_t layer)
{
tu_cs_emit(cs, iview->PITCH);
tu_cs_emit(cs, iview->layer_size >> 6);
tu_cs_emit_qw(cs, iview->base_addr + iview->layer_size * layer);
tu_cs_emit(cs, iview->view.PITCH);
tu_cs_emit(cs, iview->view.layer_size >> 6);
tu_cs_emit_qw(cs, iview->view.base_addr + iview->view.layer_size * layer);
}
void
@ -186,16 +210,16 @@ tu_cs_image_stencil_ref(struct tu_cs *cs, const struct tu_image_view *iview, uin
void
tu_cs_image_ref_2d(struct tu_cs *cs, const struct tu_image_view *iview, uint32_t layer, bool src)
{
tu_cs_emit_qw(cs, iview->base_addr + iview->layer_size * layer);
tu_cs_emit_qw(cs, iview->view.base_addr + iview->view.layer_size * layer);
/* SP_PS_2D_SRC_PITCH has shifted pitch field */
tu_cs_emit(cs, iview->PITCH << (src ? 9 : 0));
tu_cs_emit(cs, iview->view.PITCH << (src ? 9 : 0));
}
void
tu_cs_image_flag_ref(struct tu_cs *cs, const struct tu_image_view *iview, uint32_t layer)
{
tu_cs_emit_qw(cs, iview->ubwc_addr + iview->ubwc_layer_size * layer);
tu_cs_emit(cs, iview->FLAG_BUFFER_PITCH);
tu_cs_emit_qw(cs, iview->view.ubwc_addr + iview->view.ubwc_layer_size * layer);
tu_cs_emit(cs, iview->view.FLAG_BUFFER_PITCH);
}
void
@ -215,10 +239,72 @@ tu_image_view_init(struct tu_image_view *iview,
iview->image = image;
memset(iview->descriptor, 0, sizeof(iview->descriptor));
const struct fdl_layout *layouts[3];
struct fdl_layout *layout =
&image->layout[tu6_plane_index(image->vk_format, aspect_mask)];
layouts[0] = &image->layout[tu6_plane_index(image->vk_format, aspect_mask)];
if (aspect_mask != VK_IMAGE_ASPECT_COLOR_BIT)
format = tu6_plane_format(format, tu6_plane_index(format, aspect_mask));
if (aspect_mask == VK_IMAGE_ASPECT_COLOR_BIT &&
(format == VK_FORMAT_G8_B8R8_2PLANE_420_UNORM ||
format == VK_FORMAT_G8_B8_R8_3PLANE_420_UNORM)) {
layouts[1] = &image->layout[1];
layouts[2] = &image->layout[2];
}
struct fdl_view_args args = {};
args.iova = image->bo->iova + image->bo_offset;
args.base_array_layer = range->baseArrayLayer;
args.base_miplevel = range->baseMipLevel;
args.layer_count = tu_get_layerCount(image, range);
args.level_count = tu_get_levelCount(image, range);
args.format = tu_format_for_aspect(tu_vk_format_to_pipe_format(format),
aspect_mask);
vk_component_mapping_to_pipe_swizzle(pCreateInfo->components, args.swiz);
if (conversion) {
unsigned char conversion_swiz[4], create_swiz[4];
memcpy(create_swiz, args.swiz, sizeof(create_swiz));
vk_component_mapping_to_pipe_swizzle(conversion->components,
conversion_swiz);
util_format_compose_swizzles(create_swiz, conversion_swiz, args.swiz);
}
switch (pCreateInfo->viewType) {
case VK_IMAGE_VIEW_TYPE_1D:
case VK_IMAGE_VIEW_TYPE_1D_ARRAY:
args.type = FDL_VIEW_TYPE_1D;
break;
case VK_IMAGE_VIEW_TYPE_2D:
case VK_IMAGE_VIEW_TYPE_2D_ARRAY:
args.type = FDL_VIEW_TYPE_2D;
break;
case VK_IMAGE_VIEW_TYPE_CUBE:
case VK_IMAGE_VIEW_TYPE_CUBE_ARRAY:
args.type = FDL_VIEW_TYPE_CUBE;
break;
case VK_IMAGE_VIEW_TYPE_3D:
args.type = FDL_VIEW_TYPE_3D;
break;
default:
unreachable("unknown view type");
}
STATIC_ASSERT((unsigned)VK_CHROMA_LOCATION_COSITED_EVEN == (unsigned)FDL_CHROMA_LOCATION_COSITED_EVEN);
STATIC_ASSERT((unsigned)VK_CHROMA_LOCATION_MIDPOINT == (unsigned)FDL_CHROMA_LOCATION_MIDPOINT);
if (conversion) {
args.chroma_offsets[0] = (enum fdl_chroma_location) conversion->chroma_offsets[0];
args.chroma_offsets[1] = (enum fdl_chroma_location) conversion->chroma_offsets[1];
}
struct fdl6_view temp_view;
fdl6_view_init(&temp_view, layouts, &args, has_z24uint_s8uint);
memset(&iview->view, 0, sizeof(iview->view));
memset(iview->view.descriptor, 0, sizeof(iview->view.descriptor));
const struct fdl_layout *layout = layouts[0];
uint32_t width = u_minify(layout->width0, range->baseMipLevel);
uint32_t height = u_minify(layout->height0, range->baseMipLevel);
@ -272,7 +358,7 @@ tu_image_view_init(struct tu_image_view *iview,
/* TODO: also use this format with storage descriptor ? */
}
iview->descriptor[0] =
iview->view.descriptor[0] =
A6XX_TEX_CONST_0_TILE_MODE(fmt.tile_mode) |
COND(vk_format_is_srgb(format), A6XX_TEX_CONST_0_SRGB) |
A6XX_TEX_CONST_0_FMT(fmt_tex) |
@ -280,17 +366,17 @@ tu_image_view_init(struct tu_image_view *iview,
A6XX_TEX_CONST_0_SWAP(fmt.swap) |
tu6_texswiz(&pCreateInfo->components, conversion, format, aspect_mask, has_z24uint_s8uint) |
A6XX_TEX_CONST_0_MIPLVLS(tu_get_levelCount(image, range) - 1);
iview->descriptor[1] = A6XX_TEX_CONST_1_WIDTH(width) | A6XX_TEX_CONST_1_HEIGHT(height);
iview->descriptor[2] =
iview->view.descriptor[1] = A6XX_TEX_CONST_1_WIDTH(width) | A6XX_TEX_CONST_1_HEIGHT(height);
iview->view.descriptor[2] =
A6XX_TEX_CONST_2_PITCHALIGN(layout->pitchalign - 6) |
A6XX_TEX_CONST_2_PITCH(pitch) |
A6XX_TEX_CONST_2_TYPE(tu6_tex_type(pCreateInfo->viewType, false));
iview->descriptor[3] = A6XX_TEX_CONST_3_ARRAY_PITCH(layer_size);
iview->descriptor[4] = base_addr;
iview->descriptor[5] = (base_addr >> 32) | A6XX_TEX_CONST_5_DEPTH(depth);
iview->view.descriptor[3] = A6XX_TEX_CONST_3_ARRAY_PITCH(layer_size);
iview->view.descriptor[4] = base_addr;
iview->view.descriptor[5] = (base_addr >> 32) | A6XX_TEX_CONST_5_DEPTH(depth);
if (layout->tile_all)
iview->descriptor[3] |= A6XX_TEX_CONST_3_TILE_ALL;
iview->view.descriptor[3] |= A6XX_TEX_CONST_3_TILE_ALL;
if (format == VK_FORMAT_G8_B8R8_2PLANE_420_UNORM ||
format == VK_FORMAT_G8_B8_R8_3PLANE_420_UNORM) {
@ -298,16 +384,16 @@ tu_image_view_init(struct tu_image_view *iview,
assert(tu_get_levelCount(image, range) == 1);
if (conversion) {
if (conversion->chroma_offsets[0] == VK_CHROMA_LOCATION_MIDPOINT)
iview->descriptor[0] |= A6XX_TEX_CONST_0_CHROMA_MIDPOINT_X;
iview->view.descriptor[0] |= A6XX_TEX_CONST_0_CHROMA_MIDPOINT_X;
if (conversion->chroma_offsets[1] == VK_CHROMA_LOCATION_MIDPOINT)
iview->descriptor[0] |= A6XX_TEX_CONST_0_CHROMA_MIDPOINT_Y;
iview->view.descriptor[0] |= A6XX_TEX_CONST_0_CHROMA_MIDPOINT_Y;
}
uint64_t base_addr[3];
iview->descriptor[3] |= A6XX_TEX_CONST_3_TILE_ALL;
iview->view.descriptor[3] |= A6XX_TEX_CONST_3_TILE_ALL;
if (ubwc_enabled) {
iview->descriptor[3] |= A6XX_TEX_CONST_3_FLAG;
iview->view.descriptor[3] |= A6XX_TEX_CONST_3_FLAG;
/* no separate ubwc base, image must have the expected layout */
for (uint32_t i = 0; i < 3; i++) {
base_addr[i] = image->bo->iova + image->bo_offset +
@ -320,16 +406,17 @@ tu_image_view_init(struct tu_image_view *iview,
}
}
iview->descriptor[4] = base_addr[0];
iview->descriptor[5] |= base_addr[0] >> 32;
iview->descriptor[6] =
iview->view.descriptor[4] = base_addr[0];
iview->view.descriptor[5] |= base_addr[0] >> 32;
iview->view.descriptor[6] =
A6XX_TEX_CONST_6_PLANE_PITCH(fdl_pitch(&image->layout[1], range->baseMipLevel));
iview->descriptor[7] = base_addr[1];
iview->descriptor[8] = base_addr[1] >> 32;
iview->descriptor[9] = base_addr[2];
iview->descriptor[10] = base_addr[2] >> 32;
iview->view.descriptor[7] = base_addr[1];
iview->view.descriptor[8] = base_addr[1] >> 32;
iview->view.descriptor[9] = base_addr[2];
iview->view.descriptor[10] = base_addr[2] >> 32;
assert(pCreateInfo->viewType != VK_IMAGE_VIEW_TYPE_3D);
assert(memcmp(&temp_view, &iview->view, sizeof(temp_view)) == 0);
return;
}
@ -337,22 +424,22 @@ tu_image_view_init(struct tu_image_view *iview,
uint32_t block_width, block_height;
fdl6_get_ubwc_blockwidth(layout, &block_width, &block_height);
iview->descriptor[3] |= A6XX_TEX_CONST_3_FLAG;
iview->descriptor[7] = ubwc_addr;
iview->descriptor[8] = ubwc_addr >> 32;
iview->descriptor[9] |= A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH(layout->ubwc_layer_size >> 2);
iview->descriptor[10] |=
iview->view.descriptor[3] |= A6XX_TEX_CONST_3_FLAG;
iview->view.descriptor[7] = ubwc_addr;
iview->view.descriptor[8] = ubwc_addr >> 32;
iview->view.descriptor[9] |= A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH(layout->ubwc_layer_size >> 2);
iview->view.descriptor[10] |=
A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH(ubwc_pitch) |
A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW(util_logbase2_ceil(DIV_ROUND_UP(width, block_width))) |
A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH(util_logbase2_ceil(DIV_ROUND_UP(height, block_height)));
}
if (pCreateInfo->viewType == VK_IMAGE_VIEW_TYPE_3D) {
iview->descriptor[3] |=
iview->view.descriptor[3] |=
A6XX_TEX_CONST_3_MIN_LAYERSZ(layout->slices[image->level_count - 1].size0);
}
iview->SP_PS_2D_SRC_INFO = A6XX_SP_PS_2D_SRC_INFO(
iview->view.SP_PS_2D_SRC_INFO = A6XX_SP_PS_2D_SRC_INFO(
.color_format = fmt.fmt,
.tile_mode = fmt.tile_mode,
.color_swap = fmt.swap,
@ -364,18 +451,18 @@ tu_image_view_init(struct tu_image_view *iview,
!vk_format_is_depth_or_stencil(format),
.unk20 = 1,
.unk22 = 1).value;
iview->SP_PS_2D_SRC_SIZE =
iview->view.SP_PS_2D_SRC_SIZE =
A6XX_SP_PS_2D_SRC_SIZE(.width = width, .height = height).value;
/* note: these have same encoding for MRT and 2D (except 2D PITCH src) */
iview->PITCH = A6XX_RB_DEPTH_BUFFER_PITCH(pitch).value;
iview->FLAG_BUFFER_PITCH = A6XX_RB_DEPTH_FLAG_BUFFER_PITCH(
iview->view.PITCH = A6XX_RB_DEPTH_BUFFER_PITCH(pitch).value;
iview->view.FLAG_BUFFER_PITCH = A6XX_RB_DEPTH_FLAG_BUFFER_PITCH(
.pitch = ubwc_pitch, .array_pitch = layout->ubwc_layer_size >> 2).value;
iview->base_addr = base_addr;
iview->ubwc_addr = ubwc_addr;
iview->layer_size = layer_size;
iview->ubwc_layer_size = layout->ubwc_layer_size;
iview->view.base_addr = base_addr;
iview->view.ubwc_addr = ubwc_addr;
iview->view.layer_size = layer_size;
iview->view.ubwc_layer_size = layout->ubwc_layer_size;
/* Don't set fields that are only used for attachments/blit dest if COLOR
* is unsupported.
@ -389,56 +476,56 @@ tu_image_view_init(struct tu_image_view *iview,
if (is_d24s8 && ubwc_enabled)
cfmt.fmt = FMT6_Z24_UNORM_S8_UINT_AS_R8G8B8A8;
memset(iview->storage_descriptor, 0, sizeof(iview->storage_descriptor));
memset(iview->view.storage_descriptor, 0, sizeof(iview->view.storage_descriptor));
iview->storage_descriptor[0] =
iview->view.storage_descriptor[0] =
A6XX_IBO_0_FMT(fmt.fmt) |
A6XX_IBO_0_TILE_MODE(fmt.tile_mode);
iview->storage_descriptor[1] =
iview->view.storage_descriptor[1] =
A6XX_IBO_1_WIDTH(width) |
A6XX_IBO_1_HEIGHT(height);
iview->storage_descriptor[2] =
iview->view.storage_descriptor[2] =
A6XX_IBO_2_PITCH(pitch) |
A6XX_IBO_2_TYPE(tu6_tex_type(pCreateInfo->viewType, true));
iview->storage_descriptor[3] = A6XX_IBO_3_ARRAY_PITCH(layer_size);
iview->view.storage_descriptor[3] = A6XX_IBO_3_ARRAY_PITCH(layer_size);
iview->storage_descriptor[4] = base_addr;
iview->storage_descriptor[5] = (base_addr >> 32) | A6XX_IBO_5_DEPTH(storage_depth);
iview->view.storage_descriptor[4] = base_addr;
iview->view.storage_descriptor[5] = (base_addr >> 32) | A6XX_IBO_5_DEPTH(storage_depth);
if (ubwc_enabled) {
iview->storage_descriptor[3] |= A6XX_IBO_3_FLAG | A6XX_IBO_3_UNK27;
iview->storage_descriptor[7] |= ubwc_addr;
iview->storage_descriptor[8] |= ubwc_addr >> 32;
iview->storage_descriptor[9] = A6XX_IBO_9_FLAG_BUFFER_ARRAY_PITCH(layout->ubwc_layer_size >> 2);
iview->storage_descriptor[10] =
iview->view.storage_descriptor[3] |= A6XX_IBO_3_FLAG | A6XX_IBO_3_UNK27;
iview->view.storage_descriptor[7] |= ubwc_addr;
iview->view.storage_descriptor[8] |= ubwc_addr >> 32;
iview->view.storage_descriptor[9] = A6XX_IBO_9_FLAG_BUFFER_ARRAY_PITCH(layout->ubwc_layer_size >> 2);
iview->view.storage_descriptor[10] =
A6XX_IBO_10_FLAG_BUFFER_PITCH(ubwc_pitch);
}
iview->extent.width = width;
iview->extent.height = height;
iview->need_y2_align =
iview->view.width = width;
iview->view.height = height;
iview->view.need_y2_align =
(fmt.tile_mode == TILE6_LINEAR && range->baseMipLevel != image->level_count - 1);
iview->ubwc_enabled = ubwc_enabled;
iview->view.ubwc_enabled = ubwc_enabled;
iview->RB_MRT_BUF_INFO = A6XX_RB_MRT_BUF_INFO(0,
iview->view.RB_MRT_BUF_INFO = A6XX_RB_MRT_BUF_INFO(0,
.color_tile_mode = cfmt.tile_mode,
.color_format = cfmt.fmt,
.color_swap = cfmt.swap).value;
iview->SP_FS_MRT_REG = A6XX_SP_FS_MRT_REG(0,
iview->view.SP_FS_MRT_REG = A6XX_SP_FS_MRT_REG(0,
.color_format = cfmt.fmt,
.color_sint = vk_format_is_sint(format),
.color_uint = vk_format_is_uint(format)).value;
iview->RB_2D_DST_INFO = A6XX_RB_2D_DST_INFO(
iview->view.RB_2D_DST_INFO = A6XX_RB_2D_DST_INFO(
.color_format = cfmt.fmt,
.tile_mode = cfmt.tile_mode,
.color_swap = cfmt.swap,
.flags = ubwc_enabled,
.srgb = vk_format_is_srgb(format)).value;
iview->RB_BLIT_DST_INFO = A6XX_RB_BLIT_DST_INFO(
iview->view.RB_BLIT_DST_INFO = A6XX_RB_BLIT_DST_INFO(
.tile_mode = cfmt.tile_mode,
.samples = tu_msaa_samples(layout->nr_samples),
.color_format = cfmt.fmt,
@ -452,6 +539,8 @@ tu_image_view_init(struct tu_image_view *iview,
iview->stencil_layer_size = fdl_layer_stride(layout, range->baseMipLevel);
iview->stencil_PITCH = A6XX_RB_STENCIL_BUFFER_PITCH(fdl_pitch(layout, range->baseMipLevel)).value;
}
assert(memcmp(&temp_view, &iview->view, sizeof(temp_view)) == 0);
}
bool

36
src/freedreno/vulkan/tu_private.h
View file

@ -1368,6 +1368,8 @@ tu_store_gmem_attachment(struct tu_cmd_buffer *cmd,
uint32_t a,
uint32_t gmem_a);
enum pipe_format tu_vk_format_to_pipe_format(VkFormat vk_format);
struct tu_native_format
{
enum a6xx_format fmt : 8;
@ -1443,37 +1445,7 @@ struct tu_image_view
struct tu_image *image; /**< VkImageViewCreateInfo::image */
uint64_t base_addr;
uint64_t ubwc_addr;
uint32_t layer_size;
uint32_t ubwc_layer_size;
/* used to determine if fast gmem store path can be used */
VkExtent2D extent;
bool need_y2_align;
bool ubwc_enabled;
uint32_t descriptor[A6XX_TEX_CONST_DWORDS];
/* Descriptor for use as a storage image as opposed to a sampled image.
* This has a few differences for cube maps (e.g. type).
*/
uint32_t storage_descriptor[A6XX_TEX_CONST_DWORDS];
/* pre-filled register values */
uint32_t PITCH;
uint32_t FLAG_BUFFER_PITCH;
uint32_t RB_MRT_BUF_INFO;
uint32_t SP_FS_MRT_REG;
uint32_t SP_PS_2D_SRC_INFO;
uint32_t SP_PS_2D_SRC_SIZE;
uint32_t RB_2D_DST_INFO;
uint32_t RB_BLIT_DST_INFO;
struct fdl6_view view;
/* for d32s8 separate stencil */
uint64_t stencil_base_addr;
@ -1512,7 +1484,7 @@ void
tu_cs_image_stencil_ref(struct tu_cs *cs, const struct tu_image_view *iview, uint32_t layer);
#define tu_image_view_stencil(iview, x) \
((iview->x & ~A6XX_##x##_COLOR_FORMAT__MASK) | A6XX_##x##_COLOR_FORMAT(FMT6_8_UINT))
((iview->view.x & ~A6XX_##x##_COLOR_FORMAT__MASK) | A6XX_##x##_COLOR_FORMAT(FMT6_8_UINT))
VkResult
tu_gralloc_info(struct tu_device *device,