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spirv: Update the JSON and headers

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Acked-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Iván Briano <ivan.briano@intel.com>
Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28905>
This commit is contained in:
Faith Ekstrand 2024-04-24 10:57:05 -05:00 • committed by Marge Bot
parent a09c5d55ed
commit 182877342f
4 changed files with 214 additions and 44 deletions
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2
src/compiler/spirv/GLSL.std.450.h
View file

@ -1,5 +1,5 @@
/*
** Copyright (c) 2014-2016 The Khronos Group Inc.
** Copyright (c) 2014-2024 The Khronos Group Inc.
**
** Permission is hereby granted, free of charge, to any person obtaining a copy
** of this software and/or associated documentation files (the "Materials"),

2
src/compiler/spirv/OpenCL.std.h
View file

@ -1,5 +1,5 @@
/*
** Copyright (c) 2015-2019 The Khronos Group Inc.
** Copyright (c) 2015-2024 The Khronos Group Inc.
**
** Permission is hereby granted, free of charge, to any person obtaining a copy
** of this software and/or associated documentation files (the "Materials"),

218
src/compiler/spirv/spirv.core.grammar.json
View file

@ -5050,6 +5050,70 @@
"capabilities" : [ "TextureBlockMatchQCOM" ],
"version" : "None"
},
{
"opname" : "OpImageBlockMatchWindowSSDQCOM",
"class" : "Image",
"opcode" : 4500,
"operands" : [
{ "kind" : "IdResultType" },
{ "kind" : "IdResult" },
{ "kind" : "IdRef", "name" : "'Target Sampled Image'" },
{ "kind" : "IdRef", "name" : "'Target Coordinates'" },
{ "kind" : "IdRef", "name" : "'Reference Sampled Image'" },
{ "kind" : "IdRef", "name" : "'Reference Coordinates'" },
{ "kind" : "IdRef", "name" : "'Block Size'" }
],
"capabilities" : [ "TextureBlockMatch2QCOM" ],
"version" : "None"
},
{
"opname" : "OpImageBlockMatchWindowSADQCOM",
"class" : "Image",
"opcode" : 4501,
"operands" : [
{ "kind" : "IdResultType" },
{ "kind" : "IdResult" },
{ "kind" : "IdRef", "name" : "'Target Sampled Image'" },
{ "kind" : "IdRef", "name" : "'Target Coordinates'" },
{ "kind" : "IdRef", "name" : "'Reference Sampled Image'" },
{ "kind" : "IdRef", "name" : "'Reference Coordinates'" },
{ "kind" : "IdRef", "name" : "'Block Size'" }
],
"capabilities" : [ "TextureBlockMatch2QCOM" ],
"version" : "None"
},
{
"opname" : "OpImageBlockMatchGatherSSDQCOM",
"class" : "Image",
"opcode" : 4502,
"operands" : [
{ "kind" : "IdResultType" },
{ "kind" : "IdResult" },
{ "kind" : "IdRef", "name" : "'Target Sampled Image'" },
{ "kind" : "IdRef", "name" : "'Target Coordinates'" },
{ "kind" : "IdRef", "name" : "'Reference Sampled Image'" },
{ "kind" : "IdRef", "name" : "'Reference Coordinates'" },
{ "kind" : "IdRef", "name" : "'Block Size'" }
],
"capabilities" : [ "TextureBlockMatch2QCOM" ],
"version" : "None"
},
{
"opname" : "OpImageBlockMatchGatherSADQCOM",
"class" : "Image",
"opcode" : 4503,
"operands" : [
{ "kind" : "IdResultType" },
{ "kind" : "IdResult" },
{ "kind" : "IdRef", "name" : "'Target Sampled Image'" },
{ "kind" : "IdRef", "name" : "'Target Coordinates'" },
{ "kind" : "IdRef", "name" : "'Reference Sampled Image'" },
{ "kind" : "IdRef", "name" : "'Reference Coordinates'" },
{ "kind" : "IdRef", "name" : "'Block Size'" }
],
"capabilities" : [ "TextureBlockMatch2QCOM" ],
"version" : "None"
},
{
"opname" : "OpGroupIAddNonUniformAMD",
"class" : "Group",
@ -6187,6 +6251,24 @@
"capabilities" : [ "BindlessTextureNV" ],
"version" : "None"
},
{
"opname" : "OpRawAccessChainNV",
"class" : "Memory",
"opcode" : 5398,
"operands" : [
{ "kind" : "IdResultType" },
{ "kind" : "IdResult" },
{ "kind" : "IdRef", "name" : "'Base'" },
{ "kind" : "IdRef", "name" : "'Byte stride'" },
{ "kind" : "IdRef", "name" : "'Element index'" },
{ "kind" : "IdRef", "name" : "'Byte offset'" },
{ "kind" : "RawAccessChainOperands", "quantifier" : "?" }
],
"capabilities" : [
"RawAccessChainsNV"
],
"version" : "None"
},
{
"opname" : "OpSubgroupShuffleINTEL",
"class" : "Group",
@ -6576,7 +6658,7 @@
{ "kind" : "IdMemorySemantics", "name" : "'Semantics'" },
{ "kind" : "IdRef", "name" : "'Value'" }
],
"capabilities" : [ "AtomicFloat16MinMaxEXT", "AtomicFloat32MinMaxEXT", "AtomicFloat64MinMaxEXT" ],
"capabilities" : [ "AtomicFloat16MinMaxEXT", "AtomicFloat32MinMaxEXT", "AtomicFloat64MinMaxEXT", "AtomicFloat16VectorNV" ],
"version" : "None"
},
{
@ -6591,7 +6673,7 @@
{ "kind" : "IdMemorySemantics", "name" : "'Semantics'" },
{ "kind" : "IdRef", "name" : "'Value'" }
],
"capabilities" : [ "AtomicFloat16MinMaxEXT", "AtomicFloat32MinMaxEXT", "AtomicFloat64MinMaxEXT" ],
"capabilities" : [ "AtomicFloat16MinMaxEXT", "AtomicFloat32MinMaxEXT", "AtomicFloat64MinMaxEXT", "AtomicFloat16VectorNV" ],
"version" : "None"
},
{
@ -9563,7 +9645,7 @@
{ "kind" : "IdMemorySemantics", "name" : "'Semantics'" },
{ "kind" : "IdRef", "name" : "'Value'" }
],
"capabilities" : [ "AtomicFloat16AddEXT", "AtomicFloat32AddEXT", "AtomicFloat64AddEXT" ],
"capabilities" : [ "AtomicFloat16AddEXT", "AtomicFloat32AddEXT", "AtomicFloat64AddEXT", "AtomicFloat16VectorNV" ],
"extensions" : [ "SPV_EXT_shader_atomic_float_add" ],
"version" : "None"
},
@ -10603,6 +10685,28 @@
}
]
},
{
"category" : "BitEnum",
"kind" : "RawAccessChainOperands",
"enumerants" : [
{
"enumerant" : "None",
"value" : "0x0000"
},
{
"enumerant" : "RobustnessPerComponentNV",
"value" : "0x0001",
"capabilities" : [ "RawAccessChainsNV" ],
"version" : "None"
},
{
"enumerant" : "RobustnessPerElementNV",
"value" : "0x0002",
"capabilities" : [ "RawAccessChainsNV" ],
"version" : "None"
}
]
},
{
"category" : "ValueEnum",
"kind" : "SourceLanguage",
@ -11596,6 +11700,33 @@
],
"capabilities" : [ "VectorComputeINTEL" ],
"version" : "None"
},
{
"enumerant" : "MaximumRegistersINTEL",
"value" : 6461,
"parameters" : [
{ "kind" : "LiteralInteger", "name" : "'Number of Registers'" }
],
"capabilities" : [ "RegisterLimitsINTEL" ],
"version" : "None"
},
{
"enumerant" : "MaximumRegistersIdINTEL",
"value" : 6462,
"parameters" : [
{ "kind" : "IdRef", "name" : "'Number of Registers'" }
],
"capabilities" : [ "RegisterLimitsINTEL" ],
"version" : "None"
},
{
"enumerant" : "NamedMaximumRegistersINTEL",
"value" : 6463,
"parameters" : [
{ "kind" : "NamedMaximumNumberOfRegisters", "name" : "'Named Maximum Number of Registers'" }
],
"capabilities" : [ "RegisterLimitsINTEL" ],
"version" : "None"
}
]
},
@ -12198,121 +12329,101 @@
{
"enumerant" : "R",
"value" : 0,
"capabilities" : [ "Kernel" ],
"version": "1.0"
},
{
"enumerant" : "A",
"value" : 1,
"capabilities" : [ "Kernel" ],
"version": "1.0"
},
{
"enumerant" : "RG",
"value" : 2,
"capabilities" : [ "Kernel" ],
"version": "1.0"
},
{
"enumerant" : "RA",
"value" : 3,
"capabilities" : [ "Kernel" ],
"version": "1.0"
},
{
"enumerant" : "RGB",
"value" : 4,
"capabilities" : [ "Kernel" ],
"version": "1.0"
},
{
"enumerant" : "RGBA",
"value" : 5,
"capabilities" : [ "Kernel" ],
"version": "1.0"
},
{
"enumerant" : "BGRA",
"value" : 6,
"capabilities" : [ "Kernel" ],
"version": "1.0"
},
{
"enumerant" : "ARGB",
"value" : 7,
"capabilities" : [ "Kernel" ],
"version": "1.0"
},
{
"enumerant" : "Intensity",
"value" : 8,
"capabilities" : [ "Kernel" ],
"version": "1.0"
},
{
"enumerant" : "Luminance",
"value" : 9,
"capabilities" : [ "Kernel" ],
"version": "1.0"
},
{
"enumerant" : "Rx",
"value" : 10,
"capabilities" : [ "Kernel" ],
"version": "1.0"
},
{
"enumerant" : "RGx",
"value" : 11,
"capabilities" : [ "Kernel" ],
"version": "1.0"
},
{
"enumerant" : "RGBx",
"value" : 12,
"capabilities" : [ "Kernel" ],
"version": "1.0"
},
{
"enumerant" : "Depth",
"value" : 13,
"capabilities" : [ "Kernel" ],
"version": "1.0"
},
{
"enumerant" : "DepthStencil",
"value" : 14,
"capabilities" : [ "Kernel" ],
"version": "1.0"
},
{
"enumerant" : "sRGB",
"value" : 15,
"capabilities" : [ "Kernel" ],
"version": "1.0"
},
{
"enumerant" : "sRGBx",
"value" : 16,
"capabilities" : [ "Kernel" ],
"version": "1.0"
},
{
"enumerant" : "sRGBA",
"value" : 17,
"capabilities" : [ "Kernel" ],
"version": "1.0"
},
{
"enumerant" : "sBGRA",
"value" : 18,
"capabilities" : [ "Kernel" ],
"version": "1.0"
},
{
"enumerant" : "ABGR",
"value" : 19,
"capabilities" : [ "Kernel" ],
"version": "1.0"
}
]
@ -12324,115 +12435,96 @@
{
"enumerant" : "SnormInt8",
"value" : 0,
"capabilities" : [ "Kernel" ],
"version": "1.0"
},
{
"enumerant" : "SnormInt16",
"value" : 1,
"capabilities" : [ "Kernel" ],
"version": "1.0"
},
{
"enumerant" : "UnormInt8",
"value" : 2,
"capabilities" : [ "Kernel" ],
"version": "1.0"
},
{
"enumerant" : "UnormInt16",
"value" : 3,
"capabilities" : [ "Kernel" ],
"version": "1.0"
},
{
"enumerant" : "UnormShort565",
"value" : 4,
"capabilities" : [ "Kernel" ],
"version": "1.0"
},
{
"enumerant" : "UnormShort555",
"value" : 5,
"capabilities" : [ "Kernel" ],
"version": "1.0"
},
{
"enumerant" : "UnormInt101010",
"value" : 6,
"capabilities" : [ "Kernel" ],
"version": "1.0"
},
{
"enumerant" : "SignedInt8",
"value" : 7,
"capabilities" : [ "Kernel" ],
"version": "1.0"
},
{
"enumerant" : "SignedInt16",
"value" : 8,
"capabilities" : [ "Kernel" ],
"version": "1.0"
},
{
"enumerant" : "SignedInt32",
"value" : 9,
"capabilities" : [ "Kernel" ],
"version": "1.0"
},
{
"enumerant" : "UnsignedInt8",
"value" : 10,
"capabilities" : [ "Kernel" ],
"version": "1.0"
},
{
"enumerant" : "UnsignedInt16",
"value" : 11,
"capabilities" : [ "Kernel" ],
"version": "1.0"
},
{
"enumerant" : "UnsignedInt32",
"value" : 12,
"capabilities" : [ "Kernel" ],
"version": "1.0"
},
{
"enumerant" : "HalfFloat",
"value" : 13,
"capabilities" : [ "Kernel" ],
"version": "1.0"
},
{
"enumerant" : "Float",
"value" : 14,
"capabilities" : [ "Kernel" ],
"version": "1.0"
},
{
"enumerant" : "UnormInt24",
"value" : 15,
"capabilities" : [ "Kernel" ],
"version": "1.0"
},
{
"enumerant" : "UnormInt101010_2",
"value" : 16,
"capabilities" : [ "Kernel" ],
"version": "1.0"
},
{
"enumerant" : "UnsignedIntRaw10EXT",
"value" : 19,
"capabilities" : [ "Kernel" ],
"version": "1.0"
},
{
"enumerant" : "UnsignedIntRaw12EXT",
"value" : 20,
"capabilities" : [ "Kernel" ],
"version": "1.0"
}
]
@ -13095,6 +13187,12 @@
"extensions" : [ "SPV_QCOM_image_processing" ],
"version" : "None"
},
{
"enumerant" : "BlockMatchSamplerQCOM",
"value" : 4499,
"extensions" : [ "SPV_QCOM_image_processing2" ],
"version" : "None"
},
{
"enumerant" : "ExplicitInterpAMD",
"value" : 4999,
@ -15523,6 +15621,12 @@
"extensions" : [ "SPV_QCOM_image_processing" ],
"version" : "None"
},
{
"enumerant" : "TextureBlockMatch2QCOM",
"value" : 4498,
"extensions" : [ "SPV_QCOM_image_processing2" ],
"version" : "None"
},
{
"enumerant" : "Float16ImageAMD",
"value" : 5008,
@ -16006,6 +16110,12 @@
"extensions" : [ "SPV_KHR_ray_tracing_position_fetch" ],
"version" : "None"
},
{
"enumerant" : "AtomicFloat16VectorNV",
"value" : 5404,
"extensions" : [ "SPV_NV_shader_atomic_fp16_vector" ],
"version" : "None"
},
{
"enumerant" : "RayTracingDisplacementMicromapNV",
"value" : 5409,
@ -16013,6 +16123,12 @@
"extensions" : [ "SPV_NV_displacement_micromap" ],
"version" : "None"
},
{
"enumerant" : "RawAccessChainsNV",
"value" : 5414,
"extensions" : [ "SPV_NV_raw_access_chains" ],
"version" : "None"
},
{
"enumerant" : "SubgroupShuffleINTEL",
"value" : 5568,
@ -16454,6 +16570,12 @@
"value" : 6441,
"extensions" : [ "SPV_INTEL_cache_controls" ],
"version" : "None"
},
{
"enumerant" : "RegisterLimitsINTEL",
"value" : 6460,
"extensions" : [ "SPV_INTEL_maximum_registers" ],
"version" : "None"
}
]
},
@ -16691,6 +16813,18 @@
}
]
},
{
"category" : "ValueEnum",
"kind" : "NamedMaximumNumberOfRegisters",
"enumerants" : [
{
"enumerant" : "AutoINTEL",
"value" : 0,
"capabilities" : [ "RegisterLimitsINTEL" ],
"version" : "None"
}
]
},
{
"category" : "Id",
"kind" : "IdResultType",

36
src/compiler/spirv/spirv.h
View file

@ -219,6 +219,9 @@ typedef enum SpvExecutionMode_ {
SpvExecutionModeStreamingInterfaceINTEL = 6154,
SpvExecutionModeRegisterMapInterfaceINTEL = 6160,
SpvExecutionModeNamedBarrierCountINTEL = 6417,
SpvExecutionModeMaximumRegistersINTEL = 6461,
SpvExecutionModeMaximumRegistersIdINTEL = 6462,
SpvExecutionModeNamedMaximumRegistersINTEL = 6463,
SpvExecutionModeMax = 0x7fffffff,
} SpvExecutionMode;
@ -544,6 +547,7 @@ typedef enum SpvDecoration_ {
SpvDecorationNoUnsignedWrap = 4470,
SpvDecorationWeightTextureQCOM = 4487,
SpvDecorationBlockMatchTextureQCOM = 4488,
SpvDecorationBlockMatchSamplerQCOM = 4499,
SpvDecorationExplicitInterpAMD = 4999,
SpvDecorationNodeSharesPayloadLimitsWithAMDX = 5019,
SpvDecorationNodeMaxPayloadsAMDX = 5020,
@ -1079,6 +1083,7 @@ typedef enum SpvCapability_ {
SpvCapabilityTextureSampleWeightedQCOM = 4484,
SpvCapabilityTextureBoxFilterQCOM = 4485,
SpvCapabilityTextureBlockMatchQCOM = 4486,
SpvCapabilityTextureBlockMatch2QCOM = 4498,
SpvCapabilityFloat16ImageAMD = 5008,
SpvCapabilityImageGatherBiasLodAMD = 5009,
SpvCapabilityFragmentMaskAMD = 5010,
@ -1152,7 +1157,9 @@ typedef enum SpvCapability_ {
SpvCapabilityShaderInvocationReorderNV = 5383,
SpvCapabilityBindlessTextureNV = 5390,
SpvCapabilityRayQueryPositionFetchKHR = 5391,
SpvCapabilityAtomicFloat16VectorNV = 5404,
SpvCapabilityRayTracingDisplacementMicromapNV = 5409,
SpvCapabilityRawAccessChainsNV = 5414,
SpvCapabilitySubgroupShuffleINTEL = 5568,
SpvCapabilitySubgroupBufferBlockIOINTEL = 5569,
SpvCapabilitySubgroupImageBlockIOINTEL = 5570,
@ -1226,6 +1233,7 @@ typedef enum SpvCapability_ {
SpvCapabilityGroupUniformArithmeticKHR = 6400,
SpvCapabilityMaskedGatherScatterINTEL = 6427,
SpvCapabilityCacheControlsINTEL = 6441,
SpvCapabilityRegisterLimitsINTEL = 6460,
SpvCapabilityMax = 0x7fffffff,
} SpvCapability;
@ -1394,6 +1402,23 @@ typedef enum SpvStoreCacheControl_ {
SpvStoreCacheControlMax = 0x7fffffff,
} SpvStoreCacheControl;
typedef enum SpvNamedMaximumNumberOfRegisters_ {
SpvNamedMaximumNumberOfRegistersAutoINTEL = 0,
SpvNamedMaximumNumberOfRegistersMax = 0x7fffffff,
} SpvNamedMaximumNumberOfRegisters;
typedef enum SpvRawAccessChainOperandsShift_ {
SpvRawAccessChainOperandsRobustnessPerComponentNVShift = 0,
SpvRawAccessChainOperandsRobustnessPerElementNVShift = 1,
SpvRawAccessChainOperandsMax = 0x7fffffff,
} SpvRawAccessChainOperandsShift;
typedef enum SpvRawAccessChainOperandsMask_ {
SpvRawAccessChainOperandsMaskNone = 0,
SpvRawAccessChainOperandsRobustnessPerComponentNVMask = 0x00000001,
SpvRawAccessChainOperandsRobustnessPerElementNVMask = 0x00000002,
} SpvRawAccessChainOperandsMask;
typedef enum SpvOp_ {
SpvOpNop = 0,
SpvOpUndef = 1,
@ -1783,6 +1808,10 @@ typedef enum SpvOp_ {
SpvOpImageBoxFilterQCOM = 4481,
SpvOpImageBlockMatchSSDQCOM = 4482,
SpvOpImageBlockMatchSADQCOM = 4483,
SpvOpImageBlockMatchWindowSSDQCOM = 4500,
SpvOpImageBlockMatchWindowSADQCOM = 4501,
SpvOpImageBlockMatchGatherSSDQCOM = 4502,
SpvOpImageBlockMatchGatherSADQCOM = 4503,
SpvOpGroupIAddNonUniformAMD = 5000,
SpvOpGroupFAddNonUniformAMD = 5001,
SpvOpGroupFMinNonUniformAMD = 5002,
@ -1867,6 +1896,7 @@ typedef enum SpvOp_ {
SpvOpConvertUToSampledImageNV = 5395,
SpvOpConvertSampledImageToUNV = 5396,
SpvOpSamplerImageAddressingModeNV = 5397,
SpvOpRawAccessChainNV = 5398,
SpvOpSubgroupShuffleINTEL = 5571,
SpvOpSubgroupShuffleDownINTEL = 5572,
SpvOpSubgroupShuffleUpINTEL = 5573,
@ -2516,6 +2546,10 @@ inline void SpvHasResultAndType(SpvOp opcode, bool *hasResult, bool *hasResultTy
case SpvOpImageBoxFilterQCOM: *hasResult = true; *hasResultType = true; break;
case SpvOpImageBlockMatchSSDQCOM: *hasResult = true; *hasResultType = true; break;
case SpvOpImageBlockMatchSADQCOM: *hasResult = true; *hasResultType = true; break;
case SpvOpImageBlockMatchWindowSSDQCOM: *hasResult = true; *hasResultType = true; break;
case SpvOpImageBlockMatchWindowSADQCOM: *hasResult = true; *hasResultType = true; break;
case SpvOpImageBlockMatchGatherSSDQCOM: *hasResult = true; *hasResultType = true; break;
case SpvOpImageBlockMatchGatherSADQCOM: *hasResult = true; *hasResultType = true; break;
case SpvOpGroupIAddNonUniformAMD: *hasResult = true; *hasResultType = true; break;
case SpvOpGroupFAddNonUniformAMD: *hasResult = true; *hasResultType = true; break;
case SpvOpGroupFMinNonUniformAMD: *hasResult = true; *hasResultType = true; break;
@ -2597,6 +2631,7 @@ inline void SpvHasResultAndType(SpvOp opcode, bool *hasResult, bool *hasResultTy
case SpvOpConvertUToSampledImageNV: *hasResult = true; *hasResultType = true; break;
case SpvOpConvertSampledImageToUNV: *hasResult = true; *hasResultType = true; break;
case SpvOpSamplerImageAddressingModeNV: *hasResult = false; *hasResultType = false; break;
case SpvOpRawAccessChainNV: *hasResult = true; *hasResultType = true; break;
case SpvOpSubgroupShuffleINTEL: *hasResult = true; *hasResultType = true; break;
case SpvOpSubgroupShuffleDownINTEL: *hasResult = true; *hasResultType = true; break;
case SpvOpSubgroupShuffleUpINTEL: *hasResult = true; *hasResultType = true; break;
@ -2856,3 +2891,4 @@ inline void SpvHasResultAndType(SpvOp opcode, bool *hasResult, bool *hasResultTy
#endif /* SPV_ENABLE_UTILITY_CODE */
#endif