From 181611786ccc887bcb917e3b9aeb926d8f94acc6 Mon Sep 17 00:00:00 2001 From: Alyssa Rosenzweig Date: Tue, 10 Feb 2026 19:49:46 -0500 Subject: [PATCH] brw: round up block components this ensures we don't see vec5 @load_ssbo_uniform_block_intel which requires special backend handling, instead rounding up in NIR to vec8 which the LSC can do. affects dEQP-GLES31.functional.shaders.builtin_functions.integer.bitfieldextract.ivec3_lowp_compute. Signed-off-by: Alyssa Rosenzweig Reviewed-by: Lionel Landwerlin Reviewed-by: Kenneth Graunke Part-of: --- src/intel/compiler/brw/brw_nir.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/intel/compiler/brw/brw_nir.c b/src/intel/compiler/brw/brw_nir.c index b31c0bb3014..bb0824634c8 100644 --- a/src/intel/compiler/brw/brw_nir.c +++ b/src/intel/compiler/brw/brw_nir.c @@ -2514,6 +2514,7 @@ brw_vectorize_lower_mem_access(brw_pass_tracker *pt) .modes = nir_var_mem_ubo | nir_var_mem_ssbo | nir_var_mem_global | nir_var_mem_shared | nir_var_mem_task_payload, + .round_up_components = lsc_urb_round_up_components, .callback = brw_nir_should_vectorize_mem, .robust_modes = (nir_variable_mode)0, };