fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-05-24 04:08:10 +02:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

intel/brw: Fix nir_intrinsic_load_inline_data_intel register offset calculation
Some checks are pending
macOS-CI / macOS-CI (dri) (push) Waiting to run
Details
macOS-CI / macOS-CI (xlib) (push) Waiting to run
Details

Browse source 
In case of nir_intrinsic_load_inline_data_intel it was not using base_offset to
create the uniform, instead it was using only the special BRW_INLINE_PARAM_REG
value that later will be replaced by the inline_data fixed register.

So here using base_offset for both intrinsics, adding BRW_INLINE_PARAM_REG if
nir_intrinsic_load_inline_data_intel and then in brw_shader::assign_curb_setup
checking for inst->src[i].nr >= BRW_INLINE_PARAM_REG and adjusting brw_reg by
the remaining of the subtraction with BRW_INLINE_PARAM_REG.

Fixes: 7f19814414 ("brw/nir: handle inline_data_intel more like push_data_intel")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41607>
This commit is contained in:
José Roberto de Souza 2026-05-15 12:56:08 -07:00 • committed by Marge Bot
parent 92b50b25d6
commit 180d8cb544
2 changed files with 5 additions and 5 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

7
src/intel/compiler/brw/brw_from_nir.cpp
View file

@ -5164,10 +5164,9 @@ brw_from_nir_emit_intrinsic(nir_to_brw_state &ntb,
unsigned base_offset = nir_intrinsic_base(instr);
assert(base_offset % 4 == 0 || base_offset % brw_type_size_bytes(dest.type) == 0);
brw_reg src = brw_uniform_reg(
instr->intrinsic == nir_intrinsic_load_inline_data_intel ?
BRW_INLINE_PARAM_REG : (base_offset / REG_SIZE),
dest.type);
unsigned nr = base_offset / REG_SIZE;
nr += instr->intrinsic == nir_intrinsic_load_inline_data_intel ? BRW_INLINE_PARAM_REG : 0;
brw_reg src = brw_uniform_reg(nr, dest.type);
if (nir_src_is_const(instr->src[0])) {
unsigned load_offset = nir_src_as_uint(instr->src[0]);

3
src/intel/compiler/brw/brw_shader.cpp
View file

@ -327,8 +327,9 @@ brw_shader::assign_curb_setup()
continue;
struct brw_reg brw_reg;
if (inst->src[i].nr == BRW_INLINE_PARAM_REG) {
if (inst->src[i].nr >= BRW_INLINE_PARAM_REG) {
brw_reg = cs_payload().inline_parameter;
brw_reg.nr += inst->src[i].nr - BRW_INLINE_PARAM_REG;
} else {
assert(inst->src[i].nr < 64);
used |= BITFIELD64_BIT(inst->src[i].nr);