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nak/sm50: Add encoding and legalization for dadd/dfma/dmul/dsetp
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26587>
This commit is contained in:
Faith Ekstrand
Marge Bot
parent
1f5623c557
commit
17d2b2f2cc
2 changed files with 202 additions and 0 deletions
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@ -1626,6 +1626,130 @@ impl SM50Instr {
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);
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}
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fn encode_dadd(&mut self, op: &OpDAdd) {
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match &op.srcs[1].src_ref {
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SrcRef::Zero | SrcRef::Reg(_) => {
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self.set_opcode(0x5c70);
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self.set_reg_fmod_src(20..28, 49, 45, op.srcs[1]);
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}
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SrcRef::Imm32(imm) => {
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self.set_opcode(0x3870);
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self.set_src_imm_f20(20..39, 56, *imm);
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assert!(op.srcs[1].src_mod.is_none());
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}
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SrcRef::CBuf(_) => {
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self.set_opcode(0x4c70);
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self.set_cb_fmod_src(20..39, 49, 45, op.srcs[1]);
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}
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_ => panic!("Unsupported src type"),
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}
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self.set_dst(op.dst);
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self.set_reg_fmod_src(8..16, 46, 48, op.srcs[0]);
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self.set_rnd_mode(39..41, op.rnd_mode);
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}
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fn encode_dfma(&mut self, op: &OpDFma) {
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match &op.srcs[2].src_ref {
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SrcRef::Zero | SrcRef::Reg(_) => {
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match &op.srcs[1].src_ref {
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SrcRef::Zero | SrcRef::Reg(_) => {
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self.set_opcode(0x5b70);
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self.set_reg_src_ref(20..28, op.srcs[1].src_ref);
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}
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SrcRef::Imm32(imm) => {
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self.set_opcode(0x3670);
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self.set_src_imm_f20(20..39, 56, *imm);
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assert!(op.srcs[1].src_mod.is_none());
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}
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SrcRef::CBuf(cb) => {
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self.set_opcode(0x4b70);
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self.set_src_cb(20..39, cb);
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}
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_ => panic!("Invalid dfma src1: {}", op.srcs[1]),
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}
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self.set_reg_src_ref(39..47, op.srcs[2].src_ref);
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}
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SrcRef::CBuf(cb) => {
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self.set_opcode(0x5370);
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self.set_reg_src_ref(39..47, op.srcs[1].src_ref);
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self.set_src_cb(20..39, cb);
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}
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_ => panic!("Invalid dfma src2: {}", op.srcs[2]),
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}
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self.set_dst(op.dst);
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self.set_reg_src_ref(8..16, op.srcs[0].src_ref);
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assert!(!op.srcs[0].src_mod.has_fabs());
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assert!(!op.srcs[1].src_mod.has_fabs());
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assert!(!op.srcs[2].src_mod.has_fabs());
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self.set_bit(
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48,
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op.srcs[0].src_mod.has_fneg() ^ op.srcs[1].src_mod.has_fneg(),
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);
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self.set_bit(49, op.srcs[2].src_mod.has_fneg());
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self.set_rnd_mode(50..52, op.rnd_mode);
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}
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fn encode_dmul(&mut self, op: &OpDMul) {
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match &op.srcs[1].src_ref {
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SrcRef::Zero | SrcRef::Reg(_) => {
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self.set_opcode(0x5c80);
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self.set_reg_src_ref(20..28, op.srcs[1].src_ref);
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}
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SrcRef::Imm32(imm) => {
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self.set_opcode(0x3880);
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self.set_src_imm_f20(20..39, 56, *imm);
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assert!(op.srcs[1].src_mod.is_none());
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}
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SrcRef::CBuf(cb) => {
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self.set_opcode(0x4c80);
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self.set_src_cb(20..39, cb);
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}
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_ => panic!("Invalid dmul src1: {}", op.srcs[1]),
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}
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self.set_dst(op.dst);
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self.set_reg_src_ref(8..16, op.srcs[0].src_ref);
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self.set_rnd_mode(39..41, op.rnd_mode);
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assert!(!op.srcs[0].src_mod.has_fabs());
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assert!(!op.srcs[1].src_mod.has_fabs());
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self.set_bit(
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48,
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op.srcs[0].src_mod.has_fneg() ^ op.srcs[1].src_mod.has_fneg(),
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);
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}
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fn encode_dsetp(&mut self, op: &OpDSetP) {
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match &op.srcs[1].src_ref {
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SrcRef::Zero | SrcRef::Reg(_) => {
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self.set_opcode(0x5b80);
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self.set_reg_fmod_src(20..28, 44, 6, op.srcs[1]);
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}
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SrcRef::Imm32(imm) => {
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self.set_opcode(0x3680);
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self.set_src_imm_f20(20..39, 56, *imm);
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assert!(op.srcs[1].src_mod.is_none());
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}
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SrcRef::CBuf(_) => {
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self.set_opcode(0x4b80);
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self.set_reg_fmod_src(20..39, 44, 6, op.srcs[1]);
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}
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_ => panic!("Invalid dmul src1: {}", op.srcs[1]),
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}
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self.set_pred_dst(3..6, op.dst);
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self.set_pred_dst(0..3, Dst::None); // dst1
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self.set_pred_src(39..42, 42, op.accum);
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self.set_pred_set_op(45..47, op.set_op);
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self.set_float_cmp_op(48..52, op.cmp_op);
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self.set_reg_fmod_src(8..16, 7, 43, op.srcs[0]);
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}
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fn encode_iabs(&mut self, op: &OpIAbs) {
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assert!(op.src.is_reg_or_zero());
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@ -1748,6 +1872,10 @@ impl SM50Instr {
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Op::FSet(op) => si.encode_fset(&op),
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Op::FSetP(op) => si.encode_fsetp(&op),
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Op::MuFu(op) => si.encode_mufu(&op),
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Op::DAdd(op) => si.encode_dadd(&op),
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Op::DFma(op) => si.encode_dfma(&op),
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Op::DMul(op) => si.encode_dmul(&op),
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Op::DSetP(op) => si.encode_dsetp(&op),
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Op::IAbs(op) => si.encode_iabs(&op),
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Op::IAdd2(op) => si.encode_iadd2(&op),
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Op::Mov(op) => si.encode_mov(&op),
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@ -131,6 +131,48 @@ fn copy_alu_src_if_i20_overflow(
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}
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}
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fn copy_alu_src_if_f20_overflow(
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b: &mut impl SSABuilder,
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src: &mut Src,
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src_type: SrcType,
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) {
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if src.as_imm_not_f20().is_some() {
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copy_alu_src(b, src, src_type);
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}
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}
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fn copy_alu_src_if_fabs(
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b: &mut impl SSABuilder,
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src: &mut Src,
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src_type: SrcType,
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) {
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if src.src_mod.has_fabs() {
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match src_type {
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SrcType::F32 => {
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let val = b.alloc_ssa(RegFile::GPR, 1);
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b.push_op(OpFAdd {
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dst: val.into(),
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srcs: [Src::new_zero().fneg(), *src],
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saturate: false,
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rnd_mode: FRndMode::NearestEven,
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ftz: false,
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});
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*src = val.into();
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}
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SrcType::F64 => {
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let val = b.alloc_ssa(RegFile::GPR, 2);
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b.push_op(OpDAdd {
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dst: val.into(),
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srcs: [Src::new_zero().fneg(), *src],
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rnd_mode: FRndMode::NearestEven,
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});
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*src = val.into();
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}
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_ => panic!("Invalid ffabs srouce type"),
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}
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}
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}
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fn legalize_sm50_instr(
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b: &mut impl SSABuilder,
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_bl: &impl BlockLiveness,
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@ -183,6 +225,38 @@ fn legalize_sm50_instr(
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Op::MuFu(op) => {
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copy_alu_src_if_not_reg(b, &mut op.src, SrcType::GPR);
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}
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Op::DAdd(op) => {
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let [ref mut src0, ref mut src1] = op.srcs;
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swap_srcs_if_not_reg(src0, src1);
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copy_alu_src_if_not_reg(b, src0, SrcType::F64);
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copy_alu_src_if_f20_overflow(b, src1, SrcType::F64);
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}
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Op::DFma(op) => {
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let [ref mut src0, ref mut src1, ref mut src2] = op.srcs;
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copy_alu_src_if_fabs(b, src0, SrcType::F64);
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copy_alu_src_if_fabs(b, src1, SrcType::F64);
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copy_alu_src_if_fabs(b, src2, SrcType::F64);
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swap_srcs_if_not_reg(src0, src1);
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copy_alu_src_if_not_reg(b, src0, SrcType::F64);
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copy_alu_src_if_f20_overflow(b, src1, SrcType::F64);
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copy_alu_src_if_not_reg(b, src2, SrcType::F64);
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}
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Op::DMul(op) => {
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let [ref mut src0, ref mut src1] = op.srcs;
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copy_alu_src_if_fabs(b, src0, SrcType::F64);
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copy_alu_src_if_fabs(b, src1, SrcType::F64);
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swap_srcs_if_not_reg(src0, src1);
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copy_alu_src_if_not_reg(b, src0, SrcType::F64);
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copy_alu_src_if_f20_overflow(b, src1, SrcType::F64);
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}
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Op::DSetP(op) => {
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let [ref mut src0, ref mut src1] = op.srcs;
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if swap_srcs_if_not_reg(src0, src1) {
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op.cmp_op = op.cmp_op.flip();
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}
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copy_alu_src_if_not_reg(b, src0, SrcType::F64);
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copy_alu_src_if_f20_overflow(b, src1, SrcType::F64);
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}
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Op::IAbs(op) => {
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copy_alu_src_if_not_reg(b, &mut op.src, SrcType::GPR);
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}
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