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freedreno/devices: Add num_slices

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Add num_slices param to the device info.  This will be needed for
calculating LRZ layout.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38930>
This commit is contained in:
Rob Clark 2025-12-12 06:02:08 -08:00 • committed by Marge Bot
parent 57c93d31f2
commit 17b567485a
2 changed files with 7 additions and 1 deletions
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2
src/freedreno/common/freedreno_dev_info.h
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@ -69,6 +69,8 @@ struct fd_dev_info {
uint32_t num_ccu;
};
uint32_t num_slices; /* gen8+ */
struct {
uint32_t RB_DBG_ECO_CNTL;
uint32_t RB_DBG_ECO_CNTL_blit;

6
src/freedreno/common/freedreno_devices.py
View file

@ -137,7 +137,7 @@ class A6xxGPUInfo(GPUInfo):
cs_shared_mem_size, wave_granularity, fibers_per_sp,
magic_regs, raw_magic_regs = None, highest_bank_bit = 15,
ubwc_swizzle = 0x6, macrotile_mode = 1,
threadsize_base = 64, max_waves = 16):
threadsize_base = 64, max_waves = 16, num_slices = 0):
if chip == CHIP.A6XX:
compute_lb_size = 0
else:
@ -163,6 +163,7 @@ class A6xxGPUInfo(GPUInfo):
compute_lb_size = compute_lb_size)
self.num_ccu = num_ccu
self.num_slices = num_slices
self.props = Struct()
@ -1460,6 +1461,7 @@ add_gpus([
CHIP.A8XX,
[a7xx_base, a7xx_gen3, a8xx_base],
num_ccu = 6,
num_slices = 3,
tile_align_w = 64,
tile_align_h = 32,
tile_max_w = 16384,
@ -1514,6 +1516,7 @@ add_gpus([
CHIP.A8XX,
[a7xx_base, a7xx_gen3, a8xx_base, a8xx_gen2],
num_ccu = 6,
num_slices = 3,
tile_align_w = 96,
tile_align_h = 32,
tile_max_w = 16416,
@ -1532,6 +1535,7 @@ add_gpus([
CHIP.A8XX,
[a7xx_base, a7xx_gen3, a8xx_base, a8xx_gen2],
num_ccu = 8,
num_slices = 4,
tile_align_w = 64,
tile_align_h = 64,
tile_max_w = 16384,