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anv, iris: Add Wa_16011773973 for DG2
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14212>
This commit is contained in:
Anuj Phogat
Marge Bot
parent
b1156f23a2
commit
17a1df79ba
2 changed files with 101 additions and 83 deletions
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@ -6105,6 +6105,15 @@ iris_upload_dirty_render_state(struct iris_context *ice,
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}
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}
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if ((dirty & IRIS_DIRTY_SO_DECL_LIST) && ice->state.streamout) {
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if ((dirty & IRIS_DIRTY_SO_DECL_LIST) && ice->state.streamout) {
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/* Wa_16011773973:
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* If SOL is enabled and SO_DECL state has to be programmed,
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* 1. Send 3D State SOL state with SOL disabled
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* 2. Send SO_DECL NP state
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* 3. Send 3D State SOL with SOL Enabled
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*/
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if (intel_device_info_is_dg2(&batch->screen->devinfo))
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iris_emit_cmd(batch, GENX(3DSTATE_STREAMOUT), sol);
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uint32_t *decl_list =
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uint32_t *decl_list =
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ice->state.streamout + GENX(3DSTATE_STREAMOUT_length);
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ice->state.streamout + GENX(3DSTATE_STREAMOUT_length);
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iris_batch_emit(batch, decl_list, 4 * ((decl_list[0] & 0xff) + 2));
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iris_batch_emit(batch, decl_list, 4 * ((decl_list[0] & 0xff) + 2));
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@ -1523,89 +1523,6 @@ emit_3dstate_streamout(struct anv_graphics_pipeline *pipeline,
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else
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else
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xfb_info = pipeline->shaders[MESA_SHADER_VERTEX]->xfb_info;
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xfb_info = pipeline->shaders[MESA_SHADER_VERTEX]->xfb_info;
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#if GFX_VER == 7
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# define streamout_state_dw pipeline->gfx7.streamout_state
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#else
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# define streamout_state_dw pipeline->gfx8.streamout_state
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#endif
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struct GENX(3DSTATE_STREAMOUT) so = {
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GENX(3DSTATE_STREAMOUT_header),
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.RenderingDisable =
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(dynamic_states & ANV_CMD_DIRTY_DYNAMIC_RASTERIZER_DISCARD_ENABLE) ?
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0 : rs_info->rasterizerDiscardEnable,
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};
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if (xfb_info) {
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so.SOFunctionEnable = true;
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so.SOStatisticsEnable = true;
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switch (vk_provoking_vertex_mode(rs_info)) {
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case VK_PROVOKING_VERTEX_MODE_FIRST_VERTEX_EXT:
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so.ReorderMode = LEADING;
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break;
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case VK_PROVOKING_VERTEX_MODE_LAST_VERTEX_EXT:
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so.ReorderMode = TRAILING;
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break;
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default:
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unreachable("Invalid provoking vertex mode");
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}
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const VkPipelineRasterizationStateStreamCreateInfoEXT *stream_info =
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vk_find_struct_const(rs_info, PIPELINE_RASTERIZATION_STATE_STREAM_CREATE_INFO_EXT);
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so.RenderStreamSelect = stream_info ?
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stream_info->rasterizationStream : 0;
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#if GFX_VER >= 8
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so.Buffer0SurfacePitch = xfb_info->buffers[0].stride;
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so.Buffer1SurfacePitch = xfb_info->buffers[1].stride;
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so.Buffer2SurfacePitch = xfb_info->buffers[2].stride;
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so.Buffer3SurfacePitch = xfb_info->buffers[3].stride;
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#else
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pipeline->gfx7.xfb_bo_pitch[0] = xfb_info->buffers[0].stride;
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pipeline->gfx7.xfb_bo_pitch[1] = xfb_info->buffers[1].stride;
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pipeline->gfx7.xfb_bo_pitch[2] = xfb_info->buffers[2].stride;
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pipeline->gfx7.xfb_bo_pitch[3] = xfb_info->buffers[3].stride;
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/* On Gfx7, the SO buffer enables live in 3DSTATE_STREAMOUT which
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* is a bit inconvenient because we don't know what buffers will
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* actually be enabled until draw time. We do our best here by
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* setting them based on buffers_written and we disable them
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* as-needed at draw time by setting EndAddress = BaseAddress.
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*/
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so.SOBufferEnable0 = xfb_info->buffers_written & (1 << 0);
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so.SOBufferEnable1 = xfb_info->buffers_written & (1 << 1);
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so.SOBufferEnable2 = xfb_info->buffers_written & (1 << 2);
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so.SOBufferEnable3 = xfb_info->buffers_written & (1 << 3);
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#endif
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int urb_entry_read_offset = 0;
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int urb_entry_read_length =
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(prog_data->vue_map.num_slots + 1) / 2 - urb_entry_read_offset;
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/* We always read the whole vertex. This could be reduced at some
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* point by reading less and offsetting the register index in the
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* SO_DECLs.
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*/
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so.Stream0VertexReadOffset = urb_entry_read_offset;
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so.Stream0VertexReadLength = urb_entry_read_length - 1;
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so.Stream1VertexReadOffset = urb_entry_read_offset;
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so.Stream1VertexReadLength = urb_entry_read_length - 1;
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so.Stream2VertexReadOffset = urb_entry_read_offset;
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so.Stream2VertexReadLength = urb_entry_read_length - 1;
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so.Stream3VertexReadOffset = urb_entry_read_offset;
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so.Stream3VertexReadLength = urb_entry_read_length - 1;
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}
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if (dynamic_states & ANV_CMD_DIRTY_DYNAMIC_RASTERIZER_DISCARD_ENABLE) {
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GENX(3DSTATE_STREAMOUT_pack)(NULL, streamout_state_dw, &so);
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} else {
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anv_batch_emit(&pipeline->base.batch, GENX(3DSTATE_STREAMOUT), _so)
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_so = so;
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}
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if (xfb_info) {
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if (xfb_info) {
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struct GENX(SO_DECL) so_decl[MAX_XFB_STREAMS][128];
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struct GENX(SO_DECL) so_decl[MAX_XFB_STREAMS][128];
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int next_offset[MAX_XFB_BUFFERS] = {0, 0, 0, 0};
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int next_offset[MAX_XFB_BUFFERS] = {0, 0, 0, 0};
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@ -1687,6 +1604,15 @@ emit_3dstate_streamout(struct anv_graphics_pipeline *pipeline,
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sbs[xfb_info->buffer_to_stream[b]] |= 1 << b;
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sbs[xfb_info->buffer_to_stream[b]] |= 1 << b;
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}
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}
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/* Wa_16011773973:
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* If SOL is enabled and SO_DECL state has to be programmed,
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* 1. Send 3D State SOL state with SOL disabled
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* 2. Send SO_DECL NP state
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* 3. Send 3D State SOL with SOL Enabled
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*/
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if (intel_device_info_is_dg2(&pipeline->base.device->info))
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anv_batch_emit(&pipeline->base.batch, GENX(3DSTATE_STREAMOUT), so);
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uint32_t *dw = anv_batch_emitn(&pipeline->base.batch, 3 + 2 * max_decls,
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uint32_t *dw = anv_batch_emitn(&pipeline->base.batch, 3 + 2 * max_decls,
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GENX(3DSTATE_SO_DECL_LIST),
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GENX(3DSTATE_SO_DECL_LIST),
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.StreamtoBufferSelects0 = sbs[0],
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.StreamtoBufferSelects0 = sbs[0],
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@ -1708,6 +1634,89 @@ emit_3dstate_streamout(struct anv_graphics_pipeline *pipeline,
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});
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});
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}
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}
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}
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}
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#if GFX_VER == 7
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# define streamout_state_dw pipeline->gfx7.streamout_state
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#else
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# define streamout_state_dw pipeline->gfx8.streamout_state
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#endif
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struct GENX(3DSTATE_STREAMOUT) so = {
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GENX(3DSTATE_STREAMOUT_header),
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.RenderingDisable =
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(dynamic_states & ANV_CMD_DIRTY_DYNAMIC_RASTERIZER_DISCARD_ENABLE) ?
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0 : rs_info->rasterizerDiscardEnable,
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};
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if (xfb_info) {
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so.SOFunctionEnable = true;
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so.SOStatisticsEnable = true;
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switch (vk_provoking_vertex_mode(rs_info)) {
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case VK_PROVOKING_VERTEX_MODE_FIRST_VERTEX_EXT:
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so.ReorderMode = LEADING;
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break;
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case VK_PROVOKING_VERTEX_MODE_LAST_VERTEX_EXT:
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so.ReorderMode = TRAILING;
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break;
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default:
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unreachable("Invalid provoking vertex mode");
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}
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const VkPipelineRasterizationStateStreamCreateInfoEXT *stream_info =
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vk_find_struct_const(rs_info, PIPELINE_RASTERIZATION_STATE_STREAM_CREATE_INFO_EXT);
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so.RenderStreamSelect = stream_info ?
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stream_info->rasterizationStream : 0;
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#if GFX_VER >= 8
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so.Buffer0SurfacePitch = xfb_info->buffers[0].stride;
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so.Buffer1SurfacePitch = xfb_info->buffers[1].stride;
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so.Buffer2SurfacePitch = xfb_info->buffers[2].stride;
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so.Buffer3SurfacePitch = xfb_info->buffers[3].stride;
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#else
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pipeline->gfx7.xfb_bo_pitch[0] = xfb_info->buffers[0].stride;
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pipeline->gfx7.xfb_bo_pitch[1] = xfb_info->buffers[1].stride;
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pipeline->gfx7.xfb_bo_pitch[2] = xfb_info->buffers[2].stride;
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pipeline->gfx7.xfb_bo_pitch[3] = xfb_info->buffers[3].stride;
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/* On Gfx7, the SO buffer enables live in 3DSTATE_STREAMOUT which
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* is a bit inconvenient because we don't know what buffers will
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* actually be enabled until draw time. We do our best here by
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* setting them based on buffers_written and we disable them
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* as-needed at draw time by setting EndAddress = BaseAddress.
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*/
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so.SOBufferEnable0 = xfb_info->buffers_written & (1 << 0);
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so.SOBufferEnable1 = xfb_info->buffers_written & (1 << 1);
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so.SOBufferEnable2 = xfb_info->buffers_written & (1 << 2);
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so.SOBufferEnable3 = xfb_info->buffers_written & (1 << 3);
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#endif
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int urb_entry_read_offset = 0;
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int urb_entry_read_length =
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(prog_data->vue_map.num_slots + 1) / 2 - urb_entry_read_offset;
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/* We always read the whole vertex. This could be reduced at some
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* point by reading less and offsetting the register index in the
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* SO_DECLs.
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*/
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so.Stream0VertexReadOffset = urb_entry_read_offset;
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so.Stream0VertexReadLength = urb_entry_read_length - 1;
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so.Stream1VertexReadOffset = urb_entry_read_offset;
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so.Stream1VertexReadLength = urb_entry_read_length - 1;
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so.Stream2VertexReadOffset = urb_entry_read_offset;
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so.Stream2VertexReadLength = urb_entry_read_length - 1;
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so.Stream3VertexReadOffset = urb_entry_read_offset;
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so.Stream3VertexReadLength = urb_entry_read_length - 1;
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}
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if (dynamic_states & ANV_CMD_DIRTY_DYNAMIC_RASTERIZER_DISCARD_ENABLE) {
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GENX(3DSTATE_STREAMOUT_pack)(NULL, streamout_state_dw, &so);
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} else {
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anv_batch_emit(&pipeline->base.batch, GENX(3DSTATE_STREAMOUT), _so)
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_so = so;
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}
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}
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}
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static uint32_t
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static uint32_t
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